CD2401 Intel, CD2401 Datasheet - Page 119

• Manufacturer Part Number: CD2401
• Description: Multi-protocol Communications Controller
• Manufacturer: Intel

8.4.2
8.4.3
Datasheet
Register Name: STCR
Register Description: Special Transmit Command
Default Value: x’00
Access: Byte Read/Write
Bit 7
0
Special Transmit Command Register (STCR)
Async and HDLC Modes only
The CD2401 clears STCR to ‘0’ when it accepts a host CPU command.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bits 2:0
Channel Status Register (CSR)
This status register stores the current state of the channel. It can be read by the host at any time. The
states of the RxEn and the TxEn bits are controlled by host CPU commands to the CCR.
AbortTx
Bit 6
AppdCmp
Reserved – must be ‘0’.
Abort Transmission (HDLC mode)
This bit terminates the frame currently in transmission with an abort sequence. In
DMA mode, all data up to the next EOF is discarded.
Append Complete (Asynchronous DMA mode)
This bit should be set by the host when the last addition is made to the append buffer.
Reserved – must be ‘0’.
Send Special character(s) command
Use this command in Asynchronous mode to send a user-defined special character
or special character sequence. The special character is transmitted ahead on any data
remaining in the FIFO.
Select Special Character [2:0]
Bit 5
SSPC2
0
0
0
0
1
1
1
1
Bit 4
0
Multi-Protocol Communications Controller — CD2401
SSCP1
0
0
1
1
0
0
1
1
SndSpc
Bit 3
SSPC0
0
1
0
1
0
1
0
1
SSPC2
Bit 2
Reserved
Send special character 1
Send special character 2
Send special character 3
Send special character 4
Reserved
Reserved
Reserved
Motorola Hex Address: x’12
SSPC1
Bit 1
Intel Hex Address: x’11
Function
SSPC0
Bit 0
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