CD2401 Intel, CD2401 Datasheet - Page 45

• Manufacturer Part Number: CD2401
• Description: Multi-protocol Communications Controller
• Manufacturer: Intel

5.4.1
5.4.2
Datasheet
The CD2401 can perform DMA operations in any of the supported line protocols. A special
Append mode feature can reduce host CPU overhead for asynchronous data streams. DMA
operations are channel- and direction-specific. In each channel, either the transmitter, the receiver,
or both, can be independently programmed for DMA mode by the CMR.
When the CD2401 acquires the bus for a DMA transfer, only data for one channel and in one
direction is transferred; then, bus ownership is relinquished. A maximum of 16 bytes — the depth
of the transmit and receive FIFOs — are transferred during any ownership cycle.
Whenever possible, DMA cycles are 16 bits wide, and buffers have the proper byte alignment.
Unaligned buffers are sent using only 8-bit-wide transfers. If the buffer begins on an even address
and contains an odd number of bytes, the CD2401 uses 16-bit transfers for all the words in the
buffer, except the last transfer, which is 8 bits.
If one buffer in a chain ends on an odd address, the next buffer in the chain should start on an odd
address to maintain proper alignment for the most efficient bus usage. In this case, only the last
transfer of the first buffer and the first transfer of the next buffer is 8 bits wide; all others are 16
bits.
The CD2401 can be forced to perform only byte-wide DMA operations by setting the ByteDMA
bit (DMR[3]).
Bus Acquisition Cycle
Figure 5
DMA Data Transfer
After the CD2401 acquires the bus, it pulses ADLD* once. This loads the upper 24 address bits to
the external 24-bit latch. This happens only once per DMA grant cycle. The AD[15:0] bits are
remapped to Memory Address bits MA[31:16], and A[7:0] are mapped to MA[15:8]. If during
DMA, the upper 24 bits need to change, the CD2401 relinquishes the bus and then re-acquires the
bus.
During each DMA read and write cycle, the least-significant eight memory address bits, MA[7:0]
come from A[7:0].
Figure 6 on page 46
1. CD2401 asserts BR* and waits for BGIN*.
2. When BGIN* is detected, the CD2401 can access the bus after the current bus owner
3. If BGACK* is high when BGIN* goes low, then the bus is free to access. Go to step 5.
4. If BGACK* is low when BGIN* goes low, then the bus is in use. The CD2401 waits for
5. Once the CD2401 senses that BGACK* is high, it waits for the current bus cycle to terminate
relinquishes control of the bus.
BGACK* to go high.
(DS* and DTACK* high), then asserts BGACK* by driving it low. At that time, the CD2401
‘owns’ the bus. After driving BGACK* low, the CD2401 drives BR* high.
is an example where the CD2401 was required to wait to access the bus.
is an example of one DMA access after bus is acquired.
Multi-Protocol Communications Controller — CD2401
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