CD2401 Intel, CD2401 Datasheet - Page 139

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CD2401

Manufacturer Part Number
CD2401
Description
Multi-protocol Communications Controller
Manufacturer
Intel
Datasheet
8.5.4
8.5.4.1
8.5.4.2
Datasheet
Register Name: MPILR
Register Description: Modem Priority Interrupt Match
Default Value: x’00
Access: Byte Read/Write
Register Name: MIR
Register Description: Modem Interrupt
Default Value: x’00
Access: Byte Read only
Bit 7
Bit 7
Men
Note: Bit 7 of this register always reads back as ‘0’. When each of the three PILRs is programmed with
Modem Interrupt Registers
Modem Priority Interrupt Level Register (MPILR)
This register must be initialized by the host to contain the codes that are presented on the address
bus by the host system to indicate which of the three CD2401 interrupt types (that is, modem,
transmit, or receive) is being acknowledged when IACKIN* is asserted. The CD2401 compares
bits 6:0 in this register with A[6:0] to determine if the acknowledge level is correct. The value
programmed in the MSB of this register has no effect on the IACK cycle.
MPILR must contain the code used to acknowledge modem/timer interrupts.
the same value, automatic internal prioritization is activated, with receive as the highest priority,
followed by transmit and modem.
Modem Interrupt Register (MIR)
Bit 7
Bit 6
Bit 5
Mact
Bit 6
Bit 6
Modem Enable
This bit is set by the CD2401 to initiate a modem interrupt request sequence. It is
cleared during a valid modem interrupt acknowledge cycle.
Modem Active
This bit is automatically set when Men is set and the Fair Share logic allows the
assertion of a modem interrupt request. This bit is cleared when the host CPU writes
to MEOIR.
Modem End of interrupt
This bit is automatically set when the host CPU writes to the MEOIR while in a
modem interrupt routine.
Bit 5
Bit 5
Meo
User-Assigned Priority Match Value
Bit 4
Bit 4
0
Multi-Protocol Communications Controller — CD2401
Mvct 1
Bit 3
Bit 3
Mvct 0
Bit 2
Bit 2
Motorola Hex Address: x’EF
Motorola Hex Address: x’E3
Mcn 1
Bit 1
Bit 1
Intel Hex Address: x’ED
Intel Hex Address: x’E1
Mcn 0
Bit 0
Bit 0
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