CD2401 Intel, CD2401 Datasheet - Page 130

• Manufacturer Part Number: CD2401
• Description: Multi-protocol Communications Controller
• Manufacturer: Intel

CD2401 — Multi-Protocol Communications Controller
130
Register Name: RISRl
Register Description: Receive Interrupt Status - low
Default Value: x’00
Access: Byte Read only
Timeout
Bit 7
During an interrupt service routine, the host can use this register to provide a timer value as
detailed in the REOIR. The host can load only one of the two timers in the interrupt service routine.
Asynchronous Mode
Bit 7
Bits 6:4
Bit 3
Bit 2
Bit 1
Bit 0
SCdet2
Bit 6
defined as two consecutive all-zero receive characters with the CTS* pin high. Clear
Detect mode is enabled in COR1.
Timeout
This bit indicates that the receive FIFO is empty, and no data has been received
within the receive timeout period. There is no data character associated with this sta-
tus, and no other status bits are valid if this bit is set.
Special Character Detect [2:0]
Overrun Error
This bit indicates that new data has arrived, but the CD2401 FIFO or Holding regis-
ters are full. The new data is lost and the overrun indication is flagged on the last
character received before the overrun occurred.
Parity Error
This bit indicates that a parity error occurred.
Framing Error
This bit indicates that a bad stop bit is detected.
Break
This bit indicates that a BREAK is detected.
SCdet1
Bit 5
SCdet2
0
0
0
0
1
1
SCdet1
SCdet0
Bit 4
0
0
1
1
0
1
SCdet0
0
1
0
1
0
1
Bit 3
OE
None detected.
Special character 1 matched.
Special character 2 matched.
Special character 3 matched (only if COR3[7] is
enabled).
Special character 4 matched (only if COR3[7] is
enabled).
Character is within the inclusive range of the
characters in the SCRs (only if COR3[6] is
enabled).
Special character match can be enabled for error
characters by COR7.
Bit 2
PE
Status
Motorola Hex Address: x’89
Bit 1
FE
Intel Hex Address: x’8A
Datasheet
Break
Bit 0