CD2401 Intel, CD2401 Datasheet - Page 148

• Manufacturer Part Number: CD2401
• Description: Multi-protocol Communications Controller
• Manufacturer: Intel

CD2401 — Multi-Protocol Communications Controller
8.6.5
8.6.5.1
8.6.5.2
148
Register Name: ATBADRL
Register Description: Transmit Buffer A 32-bit Address – lower word
Default Value: x’0000
Access: Word Read/Write
Register Name: ATBADRU
Register Description: Transmit Buffer A 32-bit Address – upper word
Default Value: x’0000
Access: Word Read/Write
Bit 15
Bit 15
Bit 7
Bit 7
during a receive exception interrupt to determine how much data is in the buffer. The address is the
location of the next character to be transferred to the buffer. The host needs this information to
process newly arrived data in the buffer if used in Append mode and a data timeout has occurred.
The address is also needed if an exception has occurred and a gap is to be left in the DMA buffer
(see the description of the Gap[x] bits in
information by the host. For a bus error during receive data transfer, this register provides the start
address of the transfer causing the bus error.
DMA Transmit Registers
A Transmit Buffer Address – Lower (ATBADRL) Register
A Transmit Buffer Address – Upper (ATBADRU) Register
This register holds the start addresses of the A external buffer used by the CD2401 to transmit the
next data block. This register is written by the host and copied internally to control the data transfer
from the memory to the CD2401 FIFO.
Bit 14
Bit 14
Bit 6
Bit 6
Bit 13
Bit 13
Bit 5
Bit 5
Binary Address Value, 32-bit Address bits 23:16
Binary Address Value, 32-bit Address bits 31:24
Binary Address Value, 32-bit Address bits 15:8
Binary Address Value, 32-bit Address bits 7:0
Bit 12
Bit 12
Bit 4
Bit 4
Section 8.5.2.7 on page
Bit 11
Bit 11
Bit 3
Bit 3
Bit 10
Bit 10
Bit 2
Bit 2
134) for the insertion of status
Motorola Hex Address: x’52
Motorola Hex Address: x’50
Bit 9
Bit 1
Bit 9
Bit 1
Intel Hex Address: x’50
Intel Hex Address: x’52
Datasheet
Bit 8
Bit 0
Bit 8
Bit 0