CD2401 Intel, CD2401 Datasheet - Page 159

• Manufacturer Part Number: CD2401
• Description: Multi-protocol Communications Controller
• Manufacturer: Intel

Datasheet
BUSCLK
RESET*
CLK
Figure 17. CLK/BUSCLK/RESET* Timing Relationship
During RESET* active period, BUSCLK is held low. BUSCLK will transition high and begin running at one/half CLK
frequency on the first rising edge of CLK after RESET* is released.
1.This timing assumes the following conditions: BGACK* high, DTACK* high, DS* high, and BUSCLK high.
Interrupt Acknowledge
Symbol
t
PERIOD
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
44
45
46
47
48
49
50
51
52
53
54
55
61
63
64
65
66
67
R/W* setup to CLK high
CLK high to data valid
Data setup time to CLK high
Data hold time after CLK high
Address setup time to CLK high
Address hold time after CLK high
CLK high to DTACK* low (read cycle)
CLK high to DTACK* low (write cycle)
(CS* and DS*) low to DATEN*/DATDIR* low
DS* high to DATEN*/DATDIR* tristate
DS* high to data bus tristate
DS* high to DTACK* high-impedance
CLK high to IACKIN*, DS* setup
CLK high to data valid
Address setup to IACKIN* low
Address hold after IACKIN* high
CLK high to DTACK* low
(IACKIN* and DS*) low and BUSCLK high to
DATEN* and DATDIR* low
t
1
Multi-Protocol Communications Controller — CD2401
Parameter
t
2
MIN
15
15
20
5
6
5
0
0
MAX
25
25
25
28
25
25
25
35
25
40
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