CD2401 Intel, CD2401 Datasheet - Page 38

• Manufacturer Part Number: CD2401
• Description: Multi-protocol Communications Controller
• Manufacturer: Intel

CD2401 — Multi-Protocol Communications Controller
5.2.1
5.2.2
38
Contexts and Channels
The registers in the CD2401 are grouped into Global, Virtual, and four sets of Per-Channel
registers. The CD2401 is normally in the background context, where the CAR selects the channel
number for Per-Channel registers. The interrupt context begins with the interrupt acknowledge bus
cycle, and ends with a write access to the appropriate End of Interrupt register. In the interrupt
context, only the Per-channel registers for the channel number being serviced are available; the
CAR has no effect. Most Global registers are available at all times, but some are shared by the four
channels, such as the FIFO registers. These are called Virtual registers, and must be accessed only
during an interrupt context.
Interrupt contexts can be nested so that a higher-priority interrupt service can preempt a lower
priority interrupt already in progress. The CD2401 pushes the current interrupt context onto the
stack, visible in the STK, and enters the context for the newly acknowledged interrupt. Any register
accesses are in the new interrupt context until the host does a write to the appropriate EOIR for the
top-level context. The CD2401 pops the top-level context off the stack and returns to the previous
interrupt context.
Interrupt Registers
The IER and the LIVR are Per-Channel registers. IER contains bits to enable/disable the various
interrupt sources within the CD2401. The LIVR value is output on the data bus during the interrupt
acknowledge cycle. There are sets of three Global registers that correspond to the three types of
interrupts: Receive, Transmit, and Modem. The Priority Interrupt Level registers (RPILR, TPILR,
and MPILR) are programmed to contain the value that is present on the address bus during the
interrupt acknowledge bus cycle for each type of interrupt. The Interrupt Status registers (RISR,
TISR, or MISR) are examined during the interrupt service routine to determine the cause of each
type of interrupt. TDR and RDR provide access to the FIFO buffers for each channel. These
registers must not be accessed outside of the proper interrupt context. A write operation to the End
of Interrupt registers (REOIR, TEOIR, or MEOIR) must be the last access to the CD2401 at the
end of this handler routine to return it to its background context.
Datasheet