mfr4200 Freescale Semiconductor, Inc, mfr4200 Datasheet - Page 104

• Manufacturer Part Number: mfr4200
• Description: Flexray Communication Controllers
• Manufacturer: Freescale Semiconductor, Inc

MFR4200 FlexRay Communication Controller
3.2.3.5.7
Address SSC0R=0x4C, SSC1R=0x4E, SSC2R=0x50, SSC3R=0x52, SSC4R=0x54, SSC5R=0x56, SSC6R=0x58,
SSC7R=0x5A
Reset
Slot status counters may trigger interrupts via the SSCIR register (see
Counter Incrementation Register
(see
slot status monitoring availability in different protocol states.
The controller increments the internal slot status counter whenever the slot status provided by the protocol
engine fulfills the status condition specified in the corresponding slot status counter condition register
SSCCnR. The internal slot status counter is not directly visible to the host. Depending on the value of bit
MULTCYC of the corresponding register SSCCnR (see
n Register, n = [0:7]
cycle start (MULTCYC = 0) or keeps on incrementing continuously (MULTCYC = 1).
The host always gets the value of the internal slot status counter for the previous comunication cycle
(MULTCYC = 0) or cycles (MULTCYC = 1), when accessing slot status counters SSCnR.
Slot status counters do not wraparound.
104
CNT15
CNT7
Section 3.2.3.5.10, “Slot Status Counter Interrupt Mask Register
15
rh
rh
7
0x0
Slot Status Counter n Register, n = [0:7] (SSCnR)
•
•
•
The controller provides four independent slot status monitoring
mechanisms:
CNT14
CNT6
14
rh
rh
To clear slot status counter SSCnR, the host must reset bit MULTCYC
in the corresponding slot status counter condition register SSCCnR. The
controller will then reset the internal slot status counter at the beginning
of the following cycle, and the host will get the accumulated value of the
internal slot status counter at the end of the following cycle.
The controller clears all internal slot status counters when leaving the
configuration state.
The controller clears an internal slot status counter at the beginning of
every cycle, if bit MULTCYC is 0 in the corresponding slot status
counter condition register.
6
(SSCCnR)”), the controller either clears the internal slot status counter with every
Figure 3-69. Slot Status Counter n Register, n = [0:7]
CNT13
CNT5
13
rh
rh
5
(SSCIR)”). These interrupts may be enabled via the SSCIMR register
MFR4200 Data Sheet, Rev. 0
CNT12
CNT4
12
rh
rh
4
NOTE 1
NOTE 2
Section 3.2.3.5.8, “Slot Status Counter Condition
CNT11
CNT3
11
rh
rh
3
(SSCIMR)”). Refer to
CNT10
Section 3.2.3.5.9, “Slot Status
CNT2
10
rh
rh
2
CNT9
CNT1
Freescale Semiconductor
rh
rh
9
1
Table 3-4
CNT8
CNT0
rh
rh
8
0
for