mfr4200 Freescale Semiconductor, Inc, mfr4200 Datasheet - Page 114

• Manufacturer Part Number: mfr4200
• Description: Flexray Communication Controllers
• Manufacturer: Freescale Semiconductor, Inc

MFR4200 FlexRay Communication Controller
3.2.3.6.6
Address 0x0E
Reset
This register indicates the occurrence of interrupt events. Together with IER0 (see
“Interrupt Enable Register 0
system.
Every flag has an associated interrupt enable flag in interrupt enable register 0. The ISR0 register is cleared
by a hard reset or by leaving the configuration state.
114
FATAL
TIF1
rwh
rwh
15
7
0x0
Interrupt Status Register 0 (ISR0)
•
•
•
•
EHL1
CCLR
TIF0
0
0
1
1
rwh
rwh
14
The host clears any status bit in the ISR0 by writing a '1' to the bit.
Writing a ‘0’ does not change the bit state.
The CC sets a status bit of the ISR0 again when it detects the condition
for that bit.
The host must resolve the conditions causing the RFNEIF, CHIERRIF,
TXIF, and RXIF bits to be asserted, as these flags are updated
automatically by the CC, depending on conditions related to these flags.
If the host does not resolve the conditions that lead to these flags being
asserted, the CC ignores the host’s clear operation for these bits and the
bits remain asserted.
If the host and the CC try to write the ISR0 register at the same time, the
CC operation has the higher priority.
6
MAXSYNC
EHL0
(IER0)”), it allows the module to operate in a polled or interrupt driven
CYCIF
0
1
0
1
rwh
rwh
13
5
Figure 3-78. Interrupt Status Register 0
Table 3-7. Error Handling Level Coding
MFR4200 Data Sheet, Rev. 0
Error Handling Level
RFOIF
EHLC
rwh
rwh
12
4
Green level
Yellow level
Red level
Not used
NOTE
RFNEIF
MRCE
rwh
rwh
11
3
CHIERRIF
SSINT
rwh
rwh
10
Normal Passive
2
Diagnosis Stop
Normal Active
CC state
–
Section 3.2.3.5.5,
Freescale Semiconductor
BGS
TXIF
rwh
rwh
9
1
MOCE
RXIF
rwh
rwh
8
0