mfr4200 Freescale Semiconductor, Inc, mfr4200 Datasheet - Page 109

• Manufacturer Part Number: mfr4200
• Description: Flexray Communication Controllers
• Manufacturer: Freescale Semiconductor, Inc

3.2.3.6.2
Address 0x26
Reset
This register indicates the lowest numbered transmit message buffer that has its interrupt status flag (IFLG)
and its interrupt enable (IENA) bits set. A hard reset or leaving the configuration state clear the register.
3.2.3.6.3
Address 0x12
Reset
This register holds CHI status flags. The host clears any status bit in the CHIER by writing a '1' to it;
writing a ‘0’ does not change the bit state. The CC sets a status bit in the CHIER again, when it detects the
condition for that bit. If the host and the CC try to write the CHIER register at the same time, the CC write
Freescale Semiconductor
Reserved
Reserved
ILLADR
TBLE
rwh
rwh
15
15
7
7
r
r
0x0
0x0
Transmit Buffer Interrupt Vector Register (TBIVECR)
CHI Error Register (CHIER)
•
•
•
Reserved
Reserved
NMENF
RBLE
rwh
rwh
14
14
After an IFLG has been set or cleared, the CC updates the TBIVECR
register after 1 µT.
The TBIVECR register contains valid data only if the TXIF bit is set (see
Section 3.2.3.6.6, “Interrupt Status Register 0
If there are no IFLG bits set for any transmit message buffers that have
their IENA bit set, then the CC sets the TBIVECR register to 0x0000
(IFLG, IENA — see
Configuration and Status n Register, n = [0:58]
6
6
r
r
Figure 3-74. Transmit Buffer Interrupt Vector Register
Reserved
Reserved
TBIVEC5
NMEFTS
rwh
13
13
rh
5
5
r
r
Figure 3-75. CHI Error Register
Section 3.2.3.7.2, “Message Buffer Control,
MFR4200 Data Sheet, Rev. 0
Reserved
TBIVEC4
CCPBLE
SPLME
rwh
rwh
12
12
rh
4
4
r
NOTE
Reserved
TBIVEC3
MDPLE
rwh
rwh
BB
11
11
rh
3
3
r
(ISR0)”).
(BUFCSnR)”).
Reserved
Reserved
TBIVEC2
BULE
rwh
10
10
rh
2
2
r
r
Reserved
TBIVEC1
Memory Map and Registers
EFLE
IRE
rwh
rwh
rh
9
1
9
1
r
Reserved
TBIVEC0
FBLE
FLE
rwh
rwh
rh
8
0
8
0
r
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