mfr4200 Freescale Semiconductor, Inc, mfr4200 Datasheet - Page 63

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mfr4200

Manufacturer Part Number
mfr4200
Description
Flexray Communication Controllers
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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PDB[0:7] denotes the device PartID2.
MINMR[0:3] denotes the minor release of the MFR4200 device.
MJMR[0:3] denotes the major release of the MFR4200 device.
3.2.3.1.3
Address 0x0
Reset
This read-only register contains the arbitrary value 0x0815; it is used for endianess and memory map
address offset checks.
Freescale Semiconductor
MN15
MN7
15
7
r
r
0x0815
Magic Number Register (MNR)
The MNR contains 0x0000 while the controller is initializing after leaving
the hard reset state. Only after this initialization is completed, does it contain
the value 0x0815. After the controller leaves the hard reset state, the host
must wait until the initialization is completed before reading or writing to
the controller. The initialization takes 1025 cycles (CC_CLK) after
de-assertion of the hard reset.
During the internal initialization procedure time, the host must not access
any CC register except MNR (see
Register
initialization procedure.
MN14
MN6
14
6
r
r
(MNR)”), which acknowledges the completion of the internal
MN13
MN5
13
5
r
r
Figure 3-4. Magic Number Register
MFR4200 Data Sheet, Rev. 0
MN12
MN4
12
4
r
r
NOTE
Section 3.2.3.1.3, “Magic Number
MN11
MN3
11
3
r
r
MN10
MN2
10
2
r
r
Memory Map and Registers
MN9
MN1
9
1
r
r
MN8
MN0
8
0
r
r
63

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