mfr4200 Freescale Semiconductor, Inc, mfr4200 Datasheet - Page 202

• Manufacturer Part Number: mfr4200
• Description: Flexray Communication Controllers
• Manufacturer: Freescale Semiconductor, Inc

MFR4200 FlexRay Communication Controller
In the normal passive state, the CC supports regular communication functions (reception, clock
synchronization, host interface operations, etc.), except frame transmission.
In the normal passive state:
The CC enters the normal passive state from the normal mode of operation:
The CC exits the normal passive state and enters:
3.10
3.10.1
The debug port is provided by means of two MFR4200 pins — BGT/DBG2/IF_SEL0 and
ARM/DBG1/CLK_S0. The debug port control register (see
Register
independently of each other and, therefore, the same or different output functions may be configured for
the BGT/DBG2/IF_SEL0 and ARM/DBG1/CLK_S0 pins.
202
•
•
•
•
•
•
•
•
•
•
The CC receives frames on the FlexRay bus, if configured.
The CC does not transmit any frames on the FlexRay bus.
Clock synchronization runs.
The host interface is operational.
All registers comply with the access scheme shown in
From the normal active state, if the clock synchronization failed (for more detailed information,
refer to the PWD: Clock Synchronization chapter)
The configuration state, according to the state of the CONFIG bit in the MCR0 register;
The diagnosis stop state, according to the state of the DIAGSTOP bit in the MCR0 register;
The debug state, according to the state of the DBG bit in the MCR0 register;
The sleep state, according to the state of the SLPRQ and SLPACK bits in the MCR0 register; (see
Section 3.2.3.2.1, “Module Configuration Register 0
(DBPCR)”) selects the output functions for these two pins. The functions are controlled
Debug Port
Debug Port Overview
The CC enters the normal passive state at the end of the current
communication cycle.
For a detailed description of the listen state, refer to the PWD: HW States
and Operation Modes chapter.
As the DBG1 and DBG2 signals are shared with the bus guardian output
signals on the BGT/DBG2/IF_SEL0 and ARM/DBG1/CLK pins, the debug
port pins are not accessible in applications where bus guardian devices are
connected to the MFR4200.
MFR4200 Data Sheet, Rev. 0
NOTE
NOTE
NOTE
Section 3.2.3.3.33, “Debug Port Control
(MCR0)”).
Table
3-16.
Freescale Semiconductor