mfr4200 Freescale Semiconductor, Inc, mfr4200 Datasheet - Page 121

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mfr4200

Manufacturer Part Number
mfr4200
Description
Flexray Communication Controllers
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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3.2.3.6.10
Address EID0R=0x380 … EID15R=0x39E
Reset
These registers hold the slot IDs of all sync frames received in even communication cycles and used for
clock synchronization. The CC does not change the even ID values from the end of the static part in the
even cycle to the beginning of the NIT in the odd communication cycle.
3.2.3.6.11
Address OMA0R=0x3A0 … OMA15R=0x3BE
Reset
Freescale Semiconductor
Reserved
OMA15
OMA7
ID7
15
15
rh
rh
rh
7
7
r
undefined state
undefined state
Even Sync Frame ID n Register, n = [0:15] (ESFIDnR)
Odd Measurement Channel A n Register, n = [0:15] (OMAnR)
If a CC is configured to send sync frames (see
Frame Register
it:
Reserved
OMA14
OMA6
ID6
14
14
rh
initializes the ESFID0R (or OSFID0R) with its sync frame ID,
increments EMCR or OMCR,
initializes EMA0R and EMB0R or OMA0R and EMB0R with the
following value:
rh
rh
6
6
r
NMLR * SSAPOR – TSSLR * BDR – max(DCAR,DCBR) – 4
Figure 3-83. Odd Measurement Channel A n Register, n = [0:15]
Figure 3-82. Even Sync Frame ID n Register, n = [0:15]
Reserved
OMA13
OMA5
(SYNCFR)), each time the CC clears the EMCR or OMCR,
ID5
13
13
rh
rh
rh
5
5
r
MFR4200 Data Sheet, Rev. 0
Reserved
OMA12
OMA4
ID4
12
12
rh
rh
rh
4
4
r
NOTE
Reserved
OMA11
OMA3
ID3
11
11
rh
rh
rh
3
3
r
Section 3.2.3.3.29, “Sync
OMA10
OMA2
ID10
ID2
10
10
rh
rh
rh
rh
2
2
Memory Map and Registers
OMA9
OMA1
ID9
ID1
rh
rh
rh
rh
9
1
9
1
Eqn. 3-10
OMA8
OMA0
ID8
ID0
rh
rh
rh
rh
8
0
8
0
121

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