mfr4200 Freescale Semiconductor, Inc, mfr4200 Datasheet - Page 116

• Manufacturer Part Number: mfr4200
• Description: Flexray Communication Controllers
• Manufacturer: Freescale Semiconductor, Inc

MFR4200 FlexRay Communication Controller
CYCIF — Cycle Start Interrupt Flag
This bit is set when a communication cycle starts. If enabled, an interrupt remains pending while this flag
is set.
1 – A communication cycle started.
0 – No communication cycle started.
TIF0/TIF1 — Timer Interrupt Flag 0/1
This bit is set when:
If enabled, an interrupt remains pending while this flag is set.
1 – Timer 0/1 has reached the limit.
0 – Timer 0/1 has not reached the limit.
MOCE — Missing Offset Correction error
This bit is set if an insufficient number of measurements is available for offset correction at the end of the
communication cycle (even and odd).
1 – Insufficient number of measurements available for offset correction.
0 – Sufficient number of measurements available for offset correction
BGS — Bus Guardian Status
This bit indicates bus guardian schedule monitoring errors on channel A and/or channel B. The host may
read the bus guardian status register BGSR (see
(BGSR)”) to determine on which channel the error occurred. The host may reset BGS by writing a ‘1’.
1 – Bus guardian schedule monitoring error.
0 – No bus guardian schedule monitoring error
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the result of the timer 0/1 interrupt calculation, based on the cycle base and repetition fields of the
timer interrupt configuration register 0 (see
Register 0 Cycle Set
(see
and the macrotick offset programmed in the timer interrupt configuration register 0 (see
Section 3.2.3.9.1, “Timer Interrupt Configuration Register 0 Cycle Set
current macrotick value from CMCVR (see
Register
Section 3.2.3.4.2, “Current Cycle Counter Value Register
After a hard reset, timer interrupt configuration registers are cleared. The
CC indicates timers interrupts (ISR0 = 0x00C0) immediately after the hard
reset, as the protocol engine provides cycle time and cycle counter values
equal to zero during the whole configuration state. No interrupt is indicated
to the host, as the interrupt enable register IER0 is also 0 after a hard reset.
(CMCVR)”).
(TICR0CS)”), matches the current cycle counter value in the CCCV register
MFR4200 Data Sheet, Rev. 0
Section 3.2.3.4.9, “Bus Guardian Status Register
NOTE
Section 3.2.3.9.1, “Timer Interrupt Configuration
Section 3.2.3.4.3, “Current Macrotick Counter Value
(CCCVR)”);
(TICR0CS)”) matches the
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