mfr4200 Freescale Semiconductor, Inc, mfr4200 Datasheet - Page 144

• Manufacturer Part Number: mfr4200
• Description: Flexray Communication Controllers
• Manufacturer: Freescale Semiconductor, Inc

MFR4200 FlexRay Communication Controller
Receive message buffers:
The Frame ID field contains a frame ID filtering value. A received frame is stored in the first receive
message buffer with a filter matching the received frame ID. The channel and cycle counter receive
filtering criteria must also be met.
Transmit message buffers:
The frame ID field in the message buffer is used to determine the appropriate slot for frame transmission.
The frame is transmitted in the time slot corresponding to the frame ID, provided the channel and cycle
counter criteria are also met.
Receive FIFO message buffer:
The frame ID field in each element of the receive FIFO buffer stores a received frame ID value, if the frame
is accepted by the FIFO acceptance filter and not rejected by the FIFO rejection filter and if there is no
matching dedicated receive message buffer. For more information on FIFO filters, refer to
“Filtering Related
3.3.2.2
The reserved bit R* corresponds to the reserved bit in the header of the FlexRay frame. The controller
transmits that bit within the frame header. This bit must be cleared by the host for PS V1.9/V2.0 compliant
operation.
3.3.2.3
These bits are reserved for future use and have no correlation with the R* bit.
3.3.2.4
The payload preamble bit indicates that a static frame’s payload data hold a network management vector,
and that a dynamic frame’s payload data hold a message ID, respectively.
3.3.2.5
The null frame indication bit shows the value of the null frame indication flag for received frames stored
in message receive/FIFO buffers. This bit has no function for transmit message buffers. The NULLF bit,
described in
the physical layer.
144
R* — Reserved Bit
R — Reserved Bits
PP — Payload Preamble Bit
NFI — Null Frame Indication Bit
Section 3.3.3, “Message Buffer Slot Status
During the transition from the hard reset to the configuration state, the CC
initializes the NFI bits of all buffers to ‘0’. In the normal passive and active
states, the CC receives but does not store null frames. Therefore, after the
first reception and storage of a valid receive frame’s header and payload data
to a receive message/FIFO buffer, the CC sets the NFI bit of that buffer.
From that moment on, this bit remains set.
Registers”)
MFR4200 Data Sheet, Rev. 0
NOTE
Vector”, indicates the reception of a null frame on
Freescale Semiconductor
Section 3.2.3.8,