mfr4200 Freescale Semiconductor, Inc, mfr4200 Datasheet - Page 214

• Manufacturer Part Number: mfr4200
• Description: Flexray Communication Controllers
• Manufacturer: Freescale Semiconductor, Inc

Clocks and Reset Generator
5.2
5.2.1
1
Reset state:
5.2.2
The CRG will provide a system reset on any of the following events: power-on, low voltage, or low level
detected at the RESET# pin. Entry into reset is asynchronous and does not require a clock; however, the
MFR4200 cannot sequence out of reset in functional mode without a system clock.
The CRG scans, during different periods depending on the origin of the reset source, the interface and
CLKOUT selector pins: IF_SEL[0:1] and CLK_S[0:1].
214
Pin N
PC (Pullup/down Controlled) – Register controlled internal weak pull up/down for a pin in the input mode.
PD (Pull Down) – Internal weak pull down for a pin in the input mode.
DC (Drive strength Controlled) – Register controlled drive strength for a pin in the output mode.
Z – Three-stated pin.
OD (Open Drain) – Output pin with open drain.
16
24
25
32
41
47
48
52
63
1
– All pins with the PC option have pullup/down resistors disabled.
– All pins with the DC option have full drive strength.
Functional Description
TXD_BG1/TXD1_485/
BGT/DBG2/IF_SEL0
ARM/DBG1/CLK_S0
MFR4200 Pins Relevant to the CRG
Reset Generation and CLKOUT Control
EXTAL/CC_CLK
MT/CLK_S1
ECLK_CC
Pin Name
CLKOUT
RESET#
IF_SEL1
TEST
XTAL
Table 5-1. MFR4200 Pins Relevant to the CRG
In/Out
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
MFR4200 Data Sheet, Rev. 0
Pin type
DC/PD
DC/PD
DC/PD
DC/PD
PC
DC
-
-
-
-
1
Bus guardian ARM signal / Debug strobe point signal 1 /
This pin must be tied to logic ‘0’.
Hardware reset input
Crystal driver / External clock pin
Crystal driver pin
Bus guardian tick / Debug strobe point signal 2 / Host interface
selection 0
PHY data transmitter output / RS485 data transmitter output /
Host interface selection 1
Controller clock output select signal 0
Bus guardian macrotick / Controller clock output select signal 1
HCS12 clock input
CLKOUT output, selectable as disabled or 4/10/40 MHz.
Functional Description
Freescale Semiconductor