mfr4200 Freescale Semiconductor, Inc, mfr4200 Datasheet - Page 252

• Manufacturer Part Number: mfr4200
• Description: Flexray Communication Controllers
• Manufacturer: Freescale Semiconductor, Inc

MFR4200 Protocol Implementation Document
Moreover, in Figure 7-6 (PS V1.1), and in similar drawings for nodes B and C, the state Initialize schedule
lasts until the end of the communication cycle, rather than changing in the middle of the cycle.
C.8
C.8.1
The implementation is compliant with PS V1.1.
C.8.2
The implementation is compliant with PS V1.1.
C.8.3
Figure 8-3 (PS V1.1): In MFR4200 the measurement tables are initialized during the NIT (before cycle
start, rather than after the cycle start). The entries for the even cycle are initialized in the NIT of the odd
cycle. Likewise, the measurements of the odd cycle are initialized in the NIT of the even cycle.
C.8.4
The implementation is compliant with PS V1.1.
C.8.5
The implementation is compliant with PS V1.1. However, note that the clock sync measurement values
indicated in the host interface are different from the example shown in Figure 8-8 (PS V1.1).
C.8.5.1
The implementation is compliant with PS V1.1.
C.8.5.2
In MFR4200, the table for the odd cycle measurements is initialized in the NIT of the even cycle, and vice
versa, rather than after the beginning of the even cycle.
C.8.6
Figure 8-13 (PS V1.1): MFR4200 differs slightly from this description. Startup frames are counted on a
per channel basis, with one counter for each channel, rather than one counter for both channels. For
evaluation, the maximum is taken, rather than counting a startup frame on either channel with a single
counter. Moreover, in MFR4200, the check of
correction, rather than after external offset correction.
252
Clock Synchronization
Introduction
Time Representation
Synchronization Process
Clock Startup
Time Measurement
Correction Term Calculation
Data Structure
Initialization
MFR4200 Data Sheet, Rev. 0
vOffsetCorrection
is performed before the external offset
Freescale Semiconductor