mfr4200 Freescale Semiconductor, Inc, mfr4200 Datasheet - Page 187

• Manufacturer Part Number: mfr4200
• Description: Flexray Communication Controllers
• Manufacturer: Freescale Semiconductor, Inc

Every incoming frame not matching any receive filter, but matching the programmable FIFO filters, is
stored in the FIFO buffer system. In this case, the received frame and its message buffer slot status vector
are stored in the next FIFO message buffer, including. There are two status bits in ISR0 (see the RFNEIF
and RFOIF bits in
is not empty; the other shows that a receive FIFO overrun has been detected. Interrupts are generated, if
interrupts are enabled.
There are two internal (not host accessible) index registers associated with each FIFO. The PUT index
register (PUTIDX) is used as an index to the next available location in the FIFO buffer system. When a
new frame is received, it is written into the message buffer addressed by the PUTIDX register; the PUTIDX
register is then incremented, to address the next message buffer. If the PUTIDX register is incremented
past the highest FIFO message buffer, the PUTIDX register is reset to 0. The GET index register
(GETIDX) is used to address the next FIFO buffer to be read. The GETIDX register is incremented when
unlocking one of the receive FIFO buffers. The FIFO buffer system is completely filled when the PUT
pointer (PUTIDX) reaches the value of the GET pointer (GETIDX). New incoming frames cannot be
stored in the FIFO. The FIFO overrun flag is set at the end of this frame if no error has occurred. A receive
FIFO non empty status is detected when the PUTIDX register differs from the GETIDX register. This
indicates that there is at least one received frame in the FIFO buffer system.
The PUTIDX register and the GETIDX register cannot be accessed by the host.
The FIFO empty, FIFO not empty, and FIFO overrun situations are explained in
Freescale Semiconductor
Figure 3-141. FIFO Status (Empty, Not Empty, Overrun) — Example of FIFO with Three Message Buffers
FIFO Empty
•
•
(WRITE)
PUTIDX
GETIDX
(READ)
Section 3.2.3.6.6, “Interrupt Status Register 0
The CC does not store null frames and invalid frames in FIFO.
If the CC has two channels configured, then, during the static part of
transmission, the CC stores in the FIFO first the frame received on
channel A, and then the frame received on channel B. All FIFO filtering
conditions must match for both received frames.
0
–
1
–
2
–
FIFO Not Empty
MFR4200 Data Sheet, Rev. 0
GETIDX
(READ)
0
A
(WRITE)
PUTIDX
1
–
NOTE
2
–
(ISR0)”): one shows that the receive FIFO
FIFO Overrun
(WRITE)
PUTIDX
GETIDX
PUTIDX was incremented
last + new incoming
message (which is lost)
(READ)
A
0
B
1
C
2
Figure
Receive FIFO Function
3-141.
187