mfr4200 Freescale Semiconductor, Inc, mfr4200 Datasheet - Page 107

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mfr4200

Manufacturer Part Number
mfr4200
Description
Flexray Communication Controllers
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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3.2.3.5.9
Address 0x28
Reset
This register contains one bit, SSCIRn, for each slot status counter SSCnR (see
Status Counter n Register, n = [0:7]
incremented. The register is reset on leaving the configuration state. The host may clear individually each
bit in register SSCIR by writing a ‘1’ to it.
3.2.3.5.10
Address 0x2A
Reset
Freescale Semiconductor
SSCIMR7
Reserved
SSCIR7
rwh
15
15
rw
0
7
7
r
r
0x0
0x0
Slot Status Counter Incrementation Register (SSCIR)
Slot Status Counter Interrupt Mask Register (SSCIMR)
SSCIMR6
Reserved
SSCIR6
CHCFG1
rwh
14
14
rw
0
6
6
r
r
1
1
Slot status counting is supported for the static segment only.
Figure 3-71. Slot Status Counter Incrementation Register
Figure 3-72. Slot Status Counter Interrupt Mask Register
CHCFG0
SSCIMR5
Reserved
SSCIR5
Table 3-6. Channel Configuration for SSCCnR
rwh
13
13
0
1
rw
0
5
5
r
r
(SSCnR)”). Bit SSCIRn is set when the slot status counter SSCnR is
Count for both channels only once even if the counting
condition is fulfilled for both channels
Count for both channels independently. If the counting
condition is fulfilled for both channels, count twice.
MFR4200 Data Sheet, Rev. 0
SSCIMR4
Reserved
SSCIR4
rwh
12
12
rw
0
4
4
r
r
NOTE
SSCIMR3
Reserved
SSCIR3
rwh
11
11
rw
0
3
3
r
r
Meaning
SSCIMR2
Reserved
SSCIR2
rwh
10
10
rw
0
2
2
r
r
Section 3.2.3.5.7, “Slot
SSCIMR1
Reserved
SSCIR1
Memory Map and Registers
rwh
rw
9
0
1
9
1
r
r
SSCIMR0
Reserved
SSCIR0
rwh
rw
8
0
0
8
0
r
r
107

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