mfr4200 Freescale Semiconductor, Inc, mfr4200 Datasheet - Page 115

• Manufacturer Part Number: mfr4200
• Description: Flexray Communication Controllers
• Manufacturer: Freescale Semiconductor, Inc

RXIF — Receive Interrupt Flag
This bit is set when any of the enabled (IENAn = 1) receive message buffers or the receive FIFO has
successfully received a frame. Sources of this interrupt are set IFLG bits (see
Buffer Control, Configuration and Status
(see
the RXIF flag is set.
1 – At least one receive message buffer is full.
0 – All receive message buffers are empty.
TXIF — Transmit Interrupt Flag
This read-only bit is set when any of the enabled (IENAn = 1) transmit message buffers is empty
(IFLG = 1). Sources of this interrupt are set IFLG bits (see
Configuration and Status
Section 3.2.3.5.5, “Interrupt Enable Register 0
1 – At least one transmit message buffer is empty.
0 – All transmit message buffers are full.
CHIERRIF — CHI Error Interrupt Flag
This bit is set when a CHI error is detected. Sources of this interrupt are CHI errors in the CHIER register
(see
while this flag is set.
1 – A CHI error was detected.
0 – No CHI error was detected.
RFNEIF — Receive FIFO Not Empty Interrupt Flag
This bit is set when the receive FIFO is not empty. If enabled, a FIFO not empty interrupt remains pending
while this flag is set. The flag will be cleared if the FIFO is empty and message buffer 0 is unlocked. The
CC sets this flag when the FIFO is not empty.
1 – Receive FIFO is not empty.
0 – Receive FIFO is empty.
RFOIF — Receive FIFO Overrun Interrupt Flag
This bit is set when a receive FIFO overrun occurs. If enabled, an interrupt remains pending while this flag
is set.
1 – A receive FIFO overrun has been detected.
0 – No receive FIFO overrun has occurred.
Freescale Semiconductor
Section 3.2.3.5.5, “Interrupt Enable Register 0
Section 3.2.3.6.3, “CHI Error Register
Register”) of the corresponding message buffers. If TXIE is set (see
MFR4200 Data Sheet, Rev. 0
Register”) of the corresponding message buffers. If RXIE is set
(CHIER)”). If CHIERRIF is set, an interrupt remains pending
(IER0)”), an interrupt remains pending while this flag is set.
(IER0)”), a receive interrupt remains pending while
Section 3.4.1, “Message Buffer Control,
Section 3.4.1, “Message
Memory Map and Registers
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