SCH3112I-NE SMSC [SMSC Corporation], SCH3112I-NE Datasheet - Page 107

• Manufacturer Part Number: SCH3112I-NE
• Description: LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
• Manufacturer: SMSC [SMSC Corporation]

REGISTER
ADDRESS
(Note
ADDR = 6
ADDR = 7
ADDR = 0
ADDR = 1
DLAB = 1
DLAB = 1
8.4)
Note 8.4
Note 8.5
Note 8.6
Note 8.7
Note 8.8
Note 8.9
Note 8.10 Writing a one to this bit has no effect. DMA modes are not supported in this chip.
Note 8.11 The UARTs FCR’s are shadowed UART FIFO Control Shadow Registers. See
MODEM Status Regis-
REGISTER NAME
Divisor Latch (MS)
Divisor Latch (LS)
Scratch Register
(Note
ter
8.8)
DLAB is Bit 7 of the Line Control Register (ADDR = 3).
Bit 0 is the least significant bit. It is the first bit serially transmitted or received.
When operating in the XT mode, this bit will be set any time that the transmitter shift register is empty.
This bit no longer has a pin associated with it.
When operating in the XT mode, this register is not available.
These bits are always zero in the non-FIFO mode.
Table 8.7 Register Summary for an Individual UART Channel (continued)
REGISTER
SYMBOL
MSR
SCR
DLM
DDL
rier Detect
Data Car-
(DCD)
Bit 15
BIT 7
Bit 7
Bit 7
Ring Indi-
cator (RI)
Bit 14
BIT 6
Bit 6
Bit 6
Data Set
Ready
(DSR)
BIT 5
Bit 13
Bit 5
Bit 5
Send (CTS)
Clear to
Bit 12
BIT 4
Bit 4
Bit 4
Chapter 26, Runtime Register
Delta Data
(DDCD)
Carrier
Detect
BIT 3
Bit 11
Bit 3
Bit 3
Edge Ring
Indicator
Trailing
(TERI)
Bit 10
BIT 2
Bit 2
Bit 2
Delta Data
Set Ready
(DDSR)
BIT 1
Bit 1
Bit 1
Bit 9
for more details.
Delta Clear
to Send
(DCTS)
BIT 0
Bit 8
Bit 0
Bit 0