SCH3112I-NE SMSC [SMSC Corporation], SCH3112I-NE Datasheet - Page 150
![no-image](/images/no-image-200.jpg)
SCH3112I-NE
Manufacturer Part Number
SCH3112I-NE
Description
LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
Manufacturer
SMSC [SMSC Corporation]
Datasheet
1.SCH3112I-NE.pdf
(396 pages)
- Current page: 150 of 396
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Rev 0.2 (09-28-04)
PORT 92 REGISTER
BIT
7:6
5
4
3
2
1
0
FUNCTION
Reserved. Returns 00 when read
Reserved. Returns a 1 when read
Reserved. Returns a 0 when read
Reserved. Returns a 0 when read
Reserved. Returns a 1 when read
ALT_A20 Signal control. Writing a 0 to this bit causes the ALT_A20 signal to be driven low. Writing
a 1 to this bit causes the ALT_A20 signal to be driven high.
Alternate System Reset. This read/write bit provides an alternate system reset function. This function
provides an alternate means to reset the system CPU to effect a mode switch from Protected Virtual
Address Mode to the Real Address Mode. This provides a faster means of reset than is provided by
the Keyboard controller. This bit is set to a 0 by a system reset. Writing a 1 to this bit will cause the
nALT_RST signal to pulse active (low) for a minimum of 1 µs after a delay of 500 ns. Before another
nALT_RST pulse can be generated, this bit must be written back to a 0.
Bit 0 of Port 92, which generates the nALT_RST signal, is used to reset the CPU under program
control. This signal is AND’ed together externally with the reset signal (nKBDRST) from the keyboard
controller to provide a software means of resetting the CPU. This provides a faster means of reset
than is provided by the keyboard controller. Writing a 1 to bit 0 in the Port 92 Register causes this
signal to pulse low for a minimum of 6µs, after a delay of a minimum of 14µs. Before another
nALT_RST pulse can be generated, bit 0 must be set to 0 either by a system reset of a write to Port
92. Upon reset, this signal is driven inactive high (bit 0 in the Port 92 Register is set to 0).
8042
P21
0
0
1
1
NAME
Location
Default Value
Attribute
Size
DATASHEET
LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
NGATEA20
ALT_A20
134
0
1
0
1
PORT 92
92h
24h
Read/Write
8 bits
SYSTEM
NA20M
0
1
1
1
SMSC SCH311X
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