SCH3112I-NE SMSC [SMSC Corporation], SCH3112I-NE Datasheet - Page 152

• Manufacturer Part Number: SCH3112I-NE
• Description: LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
• Manufacturer: SMSC [SMSC Corporation]

Rev 0.2 (09-28-04)
12.9
The KLATCH and MLATCH bits are located in the KRST_GA20 register, in Logical Device 7 at 0xF0.
These bits are defined as follows:
Bit[4]: MLATCH – Mouse Interrupt latch control bit. 0=MINT is the 8042 MINT ANDed with Latched
Bit[3]: KLATCH – Keyboard Interrupt latch control bit. 0=KINT is the 8042 KINT ANDed with Latched
See
The SCH311X sets the associated PME Status bits when the following conditions occur:
Keyboard Interrupt
■
■
■
These events can cause a PME to be generated if the associated PME Wake Enable register bit and
the global PME_EN bit are set. Refer to
the PME interface logic and refer to
PME Status and Enable registers.
The keyboard interrupt and mouse interrupt PMEs can be generated when the part is powered by
VCC. The keyboard data and mouse data PMEs can be generated both when the part is powered by
VCC, and when the part is powered by VTR (VCC=0).
When using the keyboard and mouse data signals for wakeup, it may be necessary to isolate the
keyboard signals (KCLK, KDAT, MCLK, MDAT) from the 8042 prior to entering certain system sleep
states. This is due to the fact that the normal operation of the 8042 can prevent the system from
entering a sleep state or trigger false PME events. The SCH311X has “isolation” bits for the keyboard
and mouse signals, which allow the keyboard and mouse data signals to go into the wakeup logic but
block the clock and data signals from the 8042. These bits may be used anytime it is necessary to
isolate the 8042 keyboard and mouse signals from the 8042 before entering a system sleep state.
See the PME_STS1 for more information.
Keyboard and Mouse PME Generation
Mouse Interrupt
Active Edge on Keyboard Data Signal (KDAT)
Active Edge on Mouse Data Signal (MDAT)
Table 25.14, “KYBD. Logical Device 7 [Logical Device Number = 0X07],” on page 288
MINT (default), 1=MINT is the latched 8042 MINT.
KINT (default), 1=KINT is the latched 8042 KINT.
description of this register.
8042
Figure 12.3 Mouse Latch
MINT
MLATCH Bit
DATASHEET
LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
RD 60
Chapter 26, "Runtime Register," on page 293
Chapter 15, "PME Support," on page 153
136
VCC
D
CLR
Q
MINT
new
for more details on
for details on the
SMSC SCH311X
Datasheet
for a