SCH3112I-NE SMSC [SMSC Corporation], SCH3112I-NE Datasheet - Page 53

• Manufacturer Part Number: SCH3112I-NE
• Description: LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
• Manufacturer: SMSC [SMSC Corporation]

LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
Datasheet
SMSC SCH311X
RESET
COND.
Bit 4 TRACK 0
Active high status of the TRK0 disk interface input.
Bit 5 STEP
Active high status of the latched STEP disk interface output pin. This bit is latched with the STEP
output going active, and is cleared with a read from the DIR register, or with a hardware or software
reset.
Bit 6 DMA REQUEST
Active high status of the DMA request pending.
Bit 7 INTERRUPT PENDING
Active high bit indicating the state of the Floppy Disk Interrupt.
STATUS REGISTER B (SRB)
Address 3F1 READ ONLY
This register is read-only and monitors the state of several disk interface pins in PS/2 and Model 30
modes. The SRB can be accessed at any time when in PS/2 mode. In the PC/AT mode the data bus
pins D0 – D7 are held in a high impedance state for a read of address 3F1.
PS/2 MODE
Bit 0 MOTOR ENABLE 0
Active high status of the MTR0 disk interface output pin. This bit is low after a hardware reset and
unaffected by a software reset.
Bit 1 Reserved
Reserved will return a zero (0) when read. This bit is low after a hardware reset and unaffected by a
software reset.
Bit 2 WRITE GATE
Active high status of the WGATE disk interface output.
Bit 3 READ DATA TOGGLE
Every inactive edge of the RDATA input causes this bit to change state.
Bit 4 WRITE DATA TOGGLE
Every inactive edge of the WDATA input causes this bit to change state.
Bit 5 DRIVE SELECT 0
Reflects the status of the Drive Select 0 bit of the DOR (address 3F2 bit 0). This bit is cleared after
a hardware reset and it is unaffected by a software reset.
7
Reserved
1
6
Reserved
1
5
DRIVE
SEL0
0
DATASHEET
4
WDATA
TOGGLE
0
37
3
RDATA
TOGGLE
0
2
WGATE
0
1
Reserved
0
Rev 0.2 (09-28-04)
0
MOT
EN0
0