SCH3112I-NE SMSC [SMSC Corporation], SCH3112I-NE Datasheet - Page 109

• Manufacturer Part Number: SCH3112I-NE
• Description: LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
• Manufacturer: SMSC [SMSC Corporation]

LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
Datasheet
SMSC SCH311X
8.1.1
8.2
Host Interface
IrDA 1.0 allows serial communication at baud rates up to 115.2 kbps. Each word is sent serially
beginning with a zero value start bit. A zero is signaled by sending a single IR pulse at the beginning
of the serial bit time. A one is signaled by sending no IR pulse during the bit time. Please refer to
the AC timing for the parameters of these pulses and the IrDA waveform.
The Amplitude Shift Keyed IR allows asynchronous serial communication at baud rates up to 19.2K
Baud. Each word is sent serially beginning with a zero value start bit. A zero is signaled by sending
a 500KHz waveform for the duration of the serial bit time. A one is signaled by sending no
transmission during the bit time. Please refer to the AC timing for the parameters of the ASK-IR
waveform.
If the Half Duplex option is chosen, there is a time-out when the direction of the transmission is
changed. This time-out starts at the last bit transferred during a transmission and blocks the receiver
input until the timeout expires. If the transmit buffer is loaded with more data before the time-out
expires, the timer is restarted after the new byte is transmitted. If data is loaded into the transmit buffer
while a character is being received, the transmission will not start until the time-out expires after the
last receive bit has been received. If the start bit of another character is received during this time-out,
the timer is restarted after the new character is received. The IR half duplex time-out is programmable
via CRF2 in Logical Device 5. This register allows the time-out to be programmed to any value
between 0 and 10msec in 100usec increments.
The following figure shows the block diagram of the IR components in the SCH311X:
IR Transmit Pin
The following description describes the state of the GP53/TXD2(IRTX) pin following a power cycle.
GP53/TXD2(IRTX) Pin. This pin defaults to the GPIO input function on a VTR POR.
The GP53/TXD2(IRTX) pin will be tristate following a VCC POR, VTR POR, Soft Reset, or PCI Reset
when it is configured for the TXD2 (IRTX) function. It will remain tristate until the UART is powered.
Once the UART is powered, the state of the pin will be determined by the UART block. If VCC>2.4V
and GP53 function is selected the pin will reflect the current state of GP53.
Note: External hardware should be implemented to protect the transceiver when the IRTX2 pin is
Multiple sharing options are available are for the SCH311X devices. Sharing an interrupt requires the
following:
1. Configure the UART to be the generator to the desired IRQ.
2. Configure other shared UARTs to use No IRQ selected.
3. Set the desired share IRQ bit.
Interrupt Sharing
tristated.
ACE UART
Registers
ACE
DATASHEET
93
Sharp ASK
IrDA SIR
COM
IR Options Register,
Bit 6
Output
MUX
IR
COM
Rev 0.2 (09-28-04)