SCH3112I-NE SMSC [SMSC Corporation], SCH3112I-NE Datasheet - Page 241

• Manufacturer Part Number: SCH3112I-NE
• Description: LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
• Manufacturer: SMSC [SMSC Corporation]

LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
Datasheet
Chapter 24 Hardware Monitoring Register Set
SMSC SCH311X
33-3Ch
Addr
Reg
10h
1Dh
1Eh
1Fh
20h
21h
22h
23h
24h
25h
26h
27h
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
30h
31h
32h
3Dh
3Eh
3Fh
40h
41h
42h
43h
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
/Write
R/WC
R/WC
Read
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
4.1
4.1
4.1
4.2
4.3
4.3
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Internal Temp (Zone 2) Reading
Remote Diode 1 (Zone 1) Temp
Remote Diode 2 (Zone 3) Temp
These registers are accessed through an index and data register scheme using the HW_Reg_INDEX
and HW_Reg_DATA registers located in the runtime register block at offset 70h and 71h from the
address programmed in Logical Device A. The Hardware Monitor Block registers are located at the
indexed address shown in
Definition for the Lock column:
Yes = Register is made read-only when the lock bit is set; No = Register is not made read-only when
the lock bit is set.
+1.5V Reading from Vccp pin
PWM1 Current Duty Cycle
PWM2 Current Duty Cycle
PWM3 Current Duty Cycle
Interrupt Status Register 1
Interrupt Status Register 2
Offset Register Ambient
SMSC Test Register
Offset Register 2
Offset Register 1
FANTACH1 MSB
FANTACH2 MSB
FANTACH3 MSB
Ready/Lock/Start
FANTACH1 LSB
FANTACH2 LSB
FANTACH3 LSB
Company ID
Reg Name
Reserved
Reserved
Reserved
Device ID
Reserved
Revision
Reading
Reading
+2.5V
VCC
12V
5V
Table 24.1 Register Summary
Table 24.1, "Register
INT23
ERR2
MSb
Bit 7
RES
RES
RES
RES
RES
15
15
15
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
DATASHEET
ERR1
Bit 6
RES
RES
RES
RES
RES
D2
14
14
14
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
225
Bit 5
RES
RES
RES
RES
AMB
RES
RES
13
13
13
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
Summary".
FANTA
Bit 4
RES
RES
RES
Vbat
RES
Mon
CH3
D1
12
12
12
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
OVRID
FANTA
Bit 3
RES
RES
RES
RES
CH2
5V
11
11
11
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
READY
FANTA
Bit 2
RES
RES
RES
VCC
RES
CH1
10
10
10
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Note 24.
LOCK
Bit 1
RES
RES
RES
Vccp
RES
RES
1
1
1
1
1
1
1
1
1
1
1
1
1
9
1
9
1
9
1
1
1
1
1
1
8
START
Bit 0
LSb
RES
RES
RES
2.5V
RES
12V
0
0
0
0
0
0
0
0
0
0
0
0
0
8
0
8
0
8
0
0
0
0
0
0
Note 24.7
Note 24.7
Note 24.7
Note 24.7
Note 24.7
Note 24.7
Note 24.9
Note 24.9
Note 24.9
Note 24.7
Default
Value
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
FFh
FFh
FFh
FFh
FFh
FFh
00h
00h
N/A
N/A
N/A
00h
8Ch
5Ch
00h
04h
00h
00h
00h
00
00
00
Rev 0.2 (09-28-04)
Note 24
Note 24
Note 24
Lock
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
.1
.1
.2