SCH3112I-NE SMSC [SMSC Corporation], SCH3112I-NE Datasheet - Page 351

• Manufacturer Part Number: SCH3112I-NE
• Description: LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
• Manufacturer: SMSC [SMSC Corporation]

LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
Datasheet
APPLICATION NOTE:
SMSC SCH311X
GP47
Default = 0x00
on VTR POR
SCH3112, SCH3114
ONLY
GP47
Default = 0x01
on VTR POR
SCH3116 ONLY
N/A
NAME
Note: When selecting an alternate function for a GPIO pin, all bits in the GPIO register must be
Note 26.18 If this pin is used for Ring Indicator wakeup, either the nRI2 event can be enabled via bit 1
Note 26.19 In order to use the P17 functions, the corresponding GPIO must be programmed for output,
Note 26.20 If the EETI function is selected for this GPIO then both a high-to-low and a low-to-high edge
Note 26.21 If the FDC function is selected on this pin (DRVDEN0) then bit 6 of the FDD Mode Register
Note 26.22 The nIO_SMI pin is inactive when the internal group SMI signal is inactive and when the
Note 26.23 Bit3 of the PME_STS5 register may be set on a VCC POR. If GP53 is configured as input,
Note 26.24 These bits are R/W but have no effect on circuit operation.
properly programmed, including in/out, polarity and output type.
Table 26.3 Detailed Runtime Register Description (continued)
in the PME_EN1 register or the GP50 PME event can be enabled via bit 0 in the PME_EN5
register.
non-invert, and push-pull output type.
will set the PME, SMI and MSC status bits.
(Configuration Register 0xF0 in Logical Device 0) will override bit 7 in the GPIO Control
Register.
selected.
SMI enable bit (EN_SMI, bit 7 of the SMI_EN2 register) is '0'. When the output buffer type
is OD, nIO_SMI pin is floating when inactive; when the output buffer type is push-pull, the
nIO_SMI pin is high when inactive.
then the corresponding PME status bits will be set on a VCC POR. These bits are R/W but
have no effect on circuit operation.
73h
(R/W)
73h
(R/W)
74-7F
(R)
OFFSET
(HEX)
REG
Bit 7 of the FDD Mode Register will also affect the pin if the FDC function is
General Purpose I/O bit 4.4
Bit[0] In/Out :
Bit[1] Polarity : =1 Invert, =0 No Invert
Bit[2] Alternate Function Select
1=GPIO
0=nPCI_RST3 (Default)
Bits[6:3] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
General Purpose I/O bit 4.4
Bit[0] In/Out :
Bit[1] Polarity : =1 Invert, =0 No Invert
Bit[2] Alternate Function Select
1=nSCOUT6
0=GPIO (Default)
Bits[6:3] Reserved
Bit[7] Output Type Select
1=Open Drain
0=Push Pull
Bits[7:0] Reserved – reads return 0
DATASHEET
=1 Input, =0 Output
=1 Input, =0 Output
335
DESCRIPTION
Rev 0.2 (09-28-04)