SCH3112I-NE SMSC [SMSC Corporation], SCH3112I-NE Datasheet - Page 224

• Manufacturer Part Number: SCH3112I-NE
• Description: LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
• Manufacturer: SMSC [SMSC Corporation]

Rev 0.2 (09-28-04)
23.13.4.1
23.13.4.2
PWM Clamp
The PWM pin has the option to be held low for 0 seconds or 2 seconds following a VCC POR. This
feature is selectable by a Vbat powered register bit in the SIO Runtime Register block.
Bit[7] of the DBLCLICK register at offset 5Bh is used to select the 0 or 2 second option.
This bit is defined as follows:
■
Following PWRGD_PS being asserted the PWM Pin will be held low until either the TRDY signal is
asserted or the delay counter expires, whichever comes first. The delay counter performs two functions
when set to the 2 second delay option.
1. Following a VTR POR & VCC POR, the BIOS has up to 2 seconds to program the hwm registers
2. Following a VCC POR only (return from sleep) the hardware requires 150.8 ms (default - see
The timing diagrams in the section titled
Operation on page 209
Forced Spinup
Spinup is a feature of the auto fan control mode. Any time the PWM pin transitions from a 0% duty
cycle to a non zero duty cycle the PWM pin will be forced high for the duration of spinup or until the
fan are spinning within normal operating parameters as determined by the Tach Limit registers. See
Spin Up on page 204
the PWRGD_PS signal transitioning high following a main (VCC) power cycle if the TRDY bit is set to
one before the PWM Clamp is released.
Notes:
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■
■
START OF SPIN-UP ON MAIN (VCC) POWER CYCLE
The PWM spin-up supports the scenario where the part is powered by VTR and the fans are powered
by a main power rail. If the start bit is not cleared on a main power cycle, then the PWM will remain
at a level that may not start the fan when the main supply ramps up. This spinup will force each PWM
into spin-up (if enabled) when the TRDY bit goes active.
START OF SPIN-UP ON STANDBY (VTR) POWER CYCLE
The two second PWM Clamping feature may be used to delay the fans from being turned on full until
the BIOS has the opportunity to program the limit and configuration registers for the auto fan control
BIT[3] ZERO_SPINUP
1=zero delay for spin up
0 = delay spinup by 2 seconds (default)
and enable autofan before the fans are turned on full. This is a noise reduction feature
Table
these values have been updated. TRDY is reset to zero on a VCC POR, which forces the Fans to
be set to FFh. If the delay counter is enabled for up to a 2 second delay, the PWMs will be held
low until the reading registers are valid. Once the registers are updated, the hardware will initiate
a forced spinup (if enabled) and enter automode. See
In this device, a forced spinup will be generated the first time TRDY is detected as a ‘1’ following
the PWRGD_PS signal transitioning from low to high (if enabled). To enable this feature, set bit[3]
of the PWMx Configuration registers to one. These registers are located at offsets 5Ch, 5Dh, and
5Eh.
If the TRDY bit is ‘1’ and cleared by software after being set to and then set again while the
PWRGD_PS signal is high, the act of TRDY being asserted will not cause a forced spinup event.
The duration of the forced spin-up time is controlled by the SPIN[2:0] bits located in the PWM x
Configuration registers (5Ch - 5Eh). The forced spinup enable bit is located in Bit[3] SUENx of the
PWMx Configuration registers. Forced Spinup defaults to disabled on a VTR POR.
23.2) to load the temperature reading registers. The TRDY signal is used to indicate when
for a more detailed description of spinup. This feature can also be initiated by
show the effect of the 2 second PWM hold-off counter on the PWM pin.
DATASHEET
LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
208
Timing Diagrams for PWM Clamp and Forced Spinup
Forced Spinup on page
208.
SMSC SCH311X
Datasheet