SCH3112I-NE SMSC [SMSC Corporation], SCH3112I-NE Datasheet - Page 95

• Manufacturer Part Number: SCH3112I-NE
• Description: LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
• Manufacturer: SMSC [SMSC Corporation]

LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
Datasheet
SMSC SCH311X
Bit 1
Setting this bit to a logic “1” clears all bytes in the RCVR FIFO and resets its counter logic to 0. The
shift register is not cleared. This bit is self-clearing.
Bit 2
Setting this bit to a logic “1” clears all bytes in the XMIT FIFO and resets its counter logic to 0. The
shift register is not cleared. This bit is self-clearing.
Bit 3
Writing to this bit has no effect on the operation of the UART. The RXRDY and TXRDY pins are not
available on this chip.
Bit 4,5
Reserved
Bit 6,7
These bits are used to set the Trigger Level For The Rcvr Fifo Interrupt.
INTERRUPT IDENTIFICATION REGISTER (IIR)
Address Offset = 2H, DLAB = X, READ
By accessing this register, the host CPU can determine the highest priority interrupt and its source.
Four levels of priority interrupt exist. They are in descending order of priority:
1. Receiver Line Status (highest priority)
2. Received Data Ready
3. Transmitter Holding Register Empty
4. MODEM Status (lowest priority)
Information indicating that a prioritized interrupt is pending and the source of that interrupt is stored in
the Interrupt Identification Register (refer to
the Serial Port freezes all interrupts and indicates the highest priority pending interrupt to the CPU.
During this CPU access, even if the Serial Port records new interrupts, the current indication does not
change until access is completed. The contents of the IIR are described below.
Bit 0
This bit can be used in either a hardwired prioritized or polled environment to indicate whether an
interrupt is pending. When bit 0 is a logic “0”, an interrupt is pending and the contents of the IIR may
be used as a pointer to the appropriate internal service routine. When bit 0 is a logic “1”, no interrupt
is pending.
Bits 1 and 2
These two bits of the IIR are used to identify the highest priority interrupt pending as indicated by the
Interrupt Control Table
Bit 3
In non-FIFO mode, this bit is a logic “0”. In FIFO mode this bit is set along with bit 2 when a timeout
interrupt is pending.
Bits 4 and 5
These bits of the IIR are always logic “0”.
Bits 6 and 7
These two bits are set when the FIFO CONTROL Register bit 0 equals 1.
(Table
8.2).
DATASHEET
79
Table 8.2 on page
80). When the CPU accesses the IIR,
Rev 0.2 (09-28-04)