SCH3112I-NE SMSC [SMSC Corporation], SCH3112I-NE Datasheet - Page 341

• Manufacturer Part Number: SCH3112I-NE
• Description: LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
• Manufacturer: SMSC [SMSC Corporation]

LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
Datasheet
SMSC SCH311X
PWR_REC
Power Recovery
Register
Default = 0xxxxx11b
Default =x00000xxb
on a Vbat POR
Default = 0xxxxxxxb
on a VCC POR and
PCI Reset
Note: x indicates
that the bit is not
effected by this
reset condition.
THIS REGISTER IS
RESERVED IN THE
SCH3116 DEVICE
PS_ON Register
default = 0x00 on a
Vbat POR
default = value
latched on Power
Failure on a VTR
POR
SCH3112 AND
SCH3114 DEVICES
ONLY.
PS_ON Register
default = 0x00 on a
Vbat POR
default = value
latched on Power
Failure on a VTR
POR
THIS REGISTER IS
RESERVED IN THE
SCH3116 DEVICE
on VTR POR
NAME
Table 26.3 Detailed Runtime Register Description (continued)
49
R/W when
bit[7] =0
(default),
except for
bit[4]
Bit[4] is a
Read-Only
bit.
Read-Only
when
bit[7]=1
4A
(R)
4A
(R)
OFFSET
(HEX)
REG
SCH3116 DEVICES
Bits[7:0] RESERVED
SCH3112 AND SCH3114 DEVICES
PS_ON Shift Register
This 8-bit register is used to read the PS_ON sample values loaded in the
shift register in A/C Power Recovery Control - Mode 2.
Bit[0] = PS_ON# sampled 0 - 0.5sec before power failure
Bit[1] = PS_ON# sampled 0.5 - 1.0sec before power failure
Bit[2] = PS_ON# sampled 1.0 - 1.5sec before power failure
Bit[3] = PS_ON# sampled 1.5 - 2.0sec before power failure
Bit[4] = PS_ON# sampled 2.0 - 2.5sec before power failure
Bit[5] = PS_ON# sampled 2.5 - 3.0sec before power failure
Bit[6] = PS_ON# sampled 3.0 - 3.5sec before power failure
Bit[7] = PS_ON# sampled 3.5 - 4.0sec before power failure
Bit definition
0=off (PS_ON# signal was high)
1=on (PS_ON# signal was low)
Note: This register is powered by Vbat
SCH3116 DEVICES
Bits[7:0] RESERVED
Note: This register is powered by Vbat
DATASHEET
325
DESCRIPTION
Rev 0.2 (09-28-04)