SCH3112I-NE SMSC [SMSC Corporation], SCH3112I-NE Datasheet - Page 263

• Manufacturer Part Number: SCH3112I-NE
• Description: LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
• Manufacturer: SMSC [SMSC Corporation]

LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
Datasheet
SMSC SCH311X
24.2.19
Register
Address
64h
65h
66h
RRX-[2:0]
000
001
010
100
101
011
110
111
Read/
Write
R/W
R/W
R/W
Ramp Rate Control bits see
seePME_STS1.
Notes:
■
■
■
■
Note: This assumes the Ramp Rate Enable bit (RRxE) is set.
Registers 64-66h: Minimum PWM Duty Cycle
These registers become read only when the Lock bit is set. Any further attempts to write to these
registers shall have no effect.
These registers specify the minimum duty cycle that the PWM will output when the measured
temperature reaches the Temperature LIMIT register setting in Auto Fan Control Mode.
RR1E, RR2E, and RR3E enable PWM Ramp Rate Control for PWM 1, 2, and 3 respectively.
RR1-2, RR1-1, and RR1-0 control ramp rate time for PWM 1
RR2-2, RR2-1, and RR2-0 control ramp rate time for PWM 2
RR3-2, RR3-1, and RR3-0 control ramp rate time for PWM 3
PWM1 Minimum Duty Cycle
PWM2 Minimum Duty Cycle
PWM3 Minimum Duty Cycle
PWM RAMP TIME
(TIME FROM 33%
DUTY CYCLE TO
100% DUTY
Register Name
CYCLE)
(SEC)
17.6
11.8
7.0
4.4
3.0
1.6
0.8
35
Table 24.12 PWM Ramp Rate Control
Table
PWM RAMP TIME
DUTY CYCLE TO
DATASHEET
(TIME FROM 0%
(MSb)
100% DUTY
Bit 7
24.12. For a description of the Ramp Rate Control logic
7
7
7
CYCLE)
17.595
10.455
(SEC)
52.53
26.52
1.275
6.63
4.59
2.55
247
Bit 6
6
6
6
Bit 5
5
5
5
(PWM STEP SIZE =
TIME PER PWM
Bit 4
4
4
4
206 msec
104 msec
69 msec
41 msec
26 msec
18 msec
10 msec
5 msec
1/255)
STEP
Bit 3
3
3
3
Bit 2
2
2
2
Bit 1
1
1
1
RAMP RATE
Rev 0.2 (09-28-04)
(LSb)
Bit 0
14.49
24.39
38.46
55.56
PWM
4.85
9.62
(HZ)
100
200
0
0
0
Default
Value
80h
80h
80h