SCH3112I-NE SMSC [SMSC Corporation], SCH3112I-NE Datasheet - Page 267

• Manufacturer Part Number: SCH3112I-NE
• Description: LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
• Manufacturer: SMSC [SMSC Corporation]

LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
Datasheet
SMSC SCH311X
24.2.24
24.2.25
24.2.26
Register
Address
Register
Address
Register
Address
7Ch
73h
74h
75h
76h
77h
78h
79h
/Write
Read
R/W
/Write
/Write
Read
Read
R/W
R/W
R/W
R/W
Register 73-78h: SMSC Test Register
These are SMSC Test registers. Writing to these registers may cause unwanted results.
Register 79h: SMSC Test Register
This is a read/write register. Writing this register may produce unwanted results.
This register becomes read only when the Lock bit is set. Any further attempts to write to this register
shall have no effect.
Register 7Ch: Special Function Register
This register becomes read only when the Lock bit is set. Any further attempts to write to this register
shall have no effect.
This register contains the following bits:
Bit[0] Reserved
Bit[1] Monitoring Mode Select
0= Continuous Monitor Mode (default)
1= Cycle Monitor Mode
Bit[2] Interrupt (nHWM_INT Pin) Enable
0=Disables nHWM_INT pin output function (default)
1=Enables nHWM_INT pin output function
Bit[3] SMSC Reserved
This is a read/write bit. Reading this bit has no effect. Writing this bit to ‘1’ may cause unwanted
results.
Bit [4] SMSC Reserved
R
R
R
Special Function
Register Name
SMSC Test Register
SMSC Test Register
SMSC Test Register
SMSC Test Register
SMSC Test Register
SMSC Test Register
SMSC Test Register
Register Name
Register Name
(MSb)
AVG2
Bit 7
AVG1
Bit 6
DATASHEET
(MSb)
(MSb)
TST7
Bit 7
Bit 7
AVG0
RES
RES
RES
RES
RES
RES
Bit 5
251
TST6
Bit 6
Bit 6
RES
RES
RES
RES
RES
RES
SMSC
Bit 4
TST5
Bit 5
Bit 5
RES
RES
RES
RES
RES
RES
SMSC
Bit 3
TST4
Bit 4
Bit 4
RES
RES
RES
RES
RES
RES
TST3
Bit 3
Bit 3
TST3
TST3
TST3
TST3
TST3
TST3
INT_E
Bit 2
N
TST2
Bit 2
Bit 2
TST2
TST2
TST2
TST2
TST2
TST2
MONMD
Bit 1
TST1
Bit 1
TST1
TST1
TST1
TST1
TST1
TST1
Bit 1
Rev 0.2 (09-28-04)
(LSb)
(LSb)
(LSb)
TST0
Bit 0
RES
Bit 0
Bit 0
TST0
TST0
TST0
TST0
TST0
TST0
Default
Default
Default
Value
Value
Value
E0h
00h
09h
09h
09h
09h
09h
09h