SCH3112I-NE SMSC [SMSC Corporation], SCH3112I-NE Datasheet - Page 165

• Manufacturer Part Number: SCH3112I-NE
• Description: LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
• Manufacturer: SMSC [SMSC Corporation]

LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
Datasheet
SMSC SCH311X
13.5
HOST OPERATION
GPx_nIOW
GPx_nIOR
WRITE
READ
Note:
The SCH311X provides GPIOs that can directly generate a PME. The polarity bit in the GPIO control
registers select the edge on these GPIO pins that will set the associated status bit in a PME Status.
For additional description of PME behavior see
is the low-to-high transition. In addition, the SCH311X provides GPIOs that can directly generate an
SMI.
The following GPIOs are dedicated wakeup GPIOs with a status and enable bit in the PME status and
enable registers:
GP21-GP22,GP27, GP32-GP33 are controlled by PME_STS1, PME_STS3, PME_EN1, PME_EN3
registers.
GP50-GP57 are controlled by PME_STS5, PME_EN5 registers.
GPIO PME and SMI Functionality
SD-bit
Data Register
Figure 13.1
implementation details.
Transparen
D-TYPE
Q
D
GPIO
Bit-n
t
LATCHED VALUE OF GPIO PIN
Q
D
is for illustration purposes only and is not intended to suggest specific
GPIO INPUT PORT
Figure 13.1 GPIO Function Illustration
Table 13.4 GPIO Read/Write Behavior
NO EFFECT
0
1
DATASHEET
149
Chapter 15, "PME Support," on page
GPIO
Configuration
Register bit-1
(Polarity)
LAST WRITE TO GPIO DATA REGISTER
BIT PLACED IN GPIO DATA REGISTER
GPIO OUTPUT PORT
GPIO
Configuration
Register bit-0
(Input/Output)
153. The default
Rev 0.2 (09-28-04)
GPIO
PIN