SCH3112I-NE SMSC [SMSC Corporation], SCH3112I-NE Datasheet - Page 55

• Manufacturer Part Number: SCH3112I-NE
• Description: LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
• Manufacturer: SMSC [SMSC Corporation]

LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
Datasheet
SMSC SCH311X
RESET
COND.
DIGITAL OUTPUT REGISTER
Bit 4
X
X
1
7
MOT EN3
0
Bit 0 and 1 DRIVE SELECT
These two bits are binary encoded for the drive selects, thereby allowing only one drive to be selected
at one time. For proper device operation, they must be programmed to 0b00.
Bit 2 nRESET
A logic “0” written to this bit resets the Floppy disk controller. This reset will remain active until a logic
“1” is written to this bit. This software reset does not affect the DSR and CCR registers, nor does it
affect the other bits of the DOR register. The minimum reset duration required is 100ns, therefore
toggling this bit by consecutive writes to this register is a valid method of issuing a software reset.
Bit 3 DMAEN
PC/AT and Model 30 Mode:
Writing this bit to logic “1” will enable the DMA and interrupt functions. This bit being a logic “0” will
disable the DMA and interrupt functions. This bit is a logic “0” after a reset and in these modes.
PS/2 Mode: In this mode the DMA and interrupt functions are always enabled. During a reset, this
bit will be cleared to a logic “0”.
Bit 4 MOTOR ENABLE 0
This bit controls the MTR0 disk interface output. A logic “1” in this bit will cause the output pin to go
active.
Bit 5 MOTOR ENABLE 1
The MTR1 disk interface output is not support in the LPC$&M262. For proper device operation this bit
must be programmed with a zero (0).
Bit1
X
0
1
6
MOT EN2
0
Bit 0
0
0
1
Table 7.2 Internal 2 Drive Decode – Normal
5
MOT EN1
0
DRIVE SELECT OUTPUTS
DRIVE
0
(ACTIVE LOW)
DATASHEET
4
MOT EN0
0
nDS0
0
1
1
39
DOR VALUE
3
DMAEN
0
1CH
2
nRESET
0
MOTOR ON OUTPUTS
(ACTIVE LOW)
1
SEL1
0
DRIVE
nMTR0
nBIT 4
nBIT 4
nBIT 4
Rev 0.2 (09-28-04)
0
DRIVE
SEL0
0