SCH3112I-NE SMSC [SMSC Corporation], SCH3112I-NE Datasheet - Page 393

• Manufacturer Part Number: SCH3112I-NE
• Description: LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
• Manufacturer: SMSC [SMSC Corporation]

LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
Datasheet
Appendix C Test Mode
SMSC SCH311X
C.1
C.1.1
I/O#1
XNOR-Chain Test Mode Overview
Board Test Mode
The SCH311X provides board test capability through the implementation of one XNOR chain and one
XOR chain. The XNOR chain is dedicated to the Super I/O portion and the Hardware Monitoring Block
of the device.
XNOR-Chain test structure allows users to confirm that all pins are in contact with the motherboard
during assembly and test operations. See
setting the state of any of the input pins to the opposite of its current state will cause the output of the
chain to toggle.
The XNOR-Chain test structure must be activated to perform these tests. When the XNOR-Chain is
activated, the SCH311X pin functions are disconnected from the device pins, which all become input
pins except for one output pin at the end of XNOR-Chain.
The tests that are performed when the XNOR-Chain test structure is activated require the board-level
test hardware to control the device pins and observe the results at the XNOR-Chain output pin.
Board test mode can be entered as follows:
On the rising (deasserting) edge of PCI_RESET#, drive LFRAME# low and drive LAD[0] low.
Exit board test mode as follows:
On the rising (deasserting) edge of PCI_RESET#, drive either LFRAME# or LAD[0] high.
See PME_STS1 for a description of this board test mode.
The PCI_RESET# pin is not included in the XNOR-Chain. The XNOR-Chain output pin# is TXD1.
See the following subsections for more details.
Pin List of XNOR Chain
Pins 1-128 on the chip are inputs to the first XNOR chain, with the exception of the following:
■
■
■
All power supply pins - HVTR, HVSS, VCC, VTR, and Vbat
VSS and AVSS
All analog inputs: Remote2-, Remote2+, Remote1-, Remote1+, VCCP_IN, +12V_IN, +5V_IN,
+2.5V_IN
I/O#2
Figure C.1 XNOR-Chain Test Structure
I/O#3
DATASHEET
377
Figure
C.1. When the chip is in the XNOR chain test mode,
I/O#n
Rev 0.2 (09-28-04)
XNor
Out