SCH3112I-NE SMSC [SMSC Corporation], SCH3112I-NE Datasheet - Page 251

• Manufacturer Part Number: SCH3112I-NE
• Description: LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
• Manufacturer: SMSC [SMSC Corporation]

LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
Datasheet
SMSC SCH311X
24.2.10
Register
Address
40h
BIT
0
1
2
3
Read/
Write
R/W
The register is used by application software to identify which version of the device has been
implemented in the given system. Based on this information, software can determine which registers
to read from and write to. Further, application software may use the current stepping to implement
work-arounds for bugs found in a specific silicon stepping.
This register is read only – a write to this register has no effect.
Register 40h: Ready/Lock/Start Monitoring
Note 24.12 This LOCK bit is cleared when PWRGD_PS is asserted.
Setting the Lock bit makes the Lock and Start bits read-only.
READY
START
OVRID
NAME
LOCK
Ready/Lock/Start
Register Name
Note 24.13
R/W
R/W
R/W
R/W
R
DEFAULT
(MSb)
Bit 7
RES
0
0
0
0
DATASHEET
Bit 6
RES
When software writes a 1 to this bit, the SCH311X enables
monitoring and PWM output control functions based on the
limit and parameter registers. Before this bit is set, the part
does not update register values. Whenever this bit is set to
0, the monitoring and PWM output control functions are
based on the default limits and parameters, regardless of
the current values in the limit and parameter registers. The
SCH311X preserves the values currently stored in the limit
and parameter registers when this bit is set or cleared. This
bit becomes read only when the Lock bit is set.
Notes:
■
■
Setting this bit to 1 locks specified limit and parameter
registers. Once this bit is set, limit and parameter registers
become read only and will remain locked until the device is
powered off. This register bit becomes read only once it is
set.
The SCH311X sets this bit automatically after the part is fully
powered up, has completed the power-up-reset process,
and after all A/D converters are functioning (all bias
conditions for the A/Ds have stabilized and the A/Ds are in
operational mode). (Always reads back ‘1’.)
If this bit is set to 1, all PWM outputs go to 100% duty cycle
regardless of whether or not the lock bit is set.
235
When this bit is 0, all fans are on full 100% duty cycle, i.e.,
PWM pins are high for 255 clocks, low for 1 clock. When
this bit is 0, the part is not monitoring.
It is suggested that software clear the START bit and exit
auto fan control mode before modifying any fan
configuration registers. After clearing the START bit,
software should wait for a period of one 90kHz-10% clock
(~12.5usec) before setting the START bit back to ‘1’ to
ensure the fan logic exited auto mode when START was
cleared.
Bit 5
RES
Bit 4
RES
OVRID
Bit 3
DESCRIPTION
READY
Bit 2
LOCK
24.12
Bit 1
Note
Rev 0.2 (09-28-04)
START
(LSb)
Bit 0
Default
Value
04h