SCH3112I-NE SMSC [SMSC Corporation], SCH3112I-NE Datasheet - Page 179

• Manufacturer Part Number: SCH3112I-NE
• Description: LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
• Manufacturer: SMSC [SMSC Corporation]

LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
Datasheet
Chapter 18 Reset Generation
SMSC SCH311X
RESGEN
default = 00h
RESGEN
1
0
The SCH311X device has a Reset Generator with the following characteristics:
■
■
■
■
■
The programming for the RESGEN function is in the REGEN register, runtime register offset 1Dh as
shown in
Output MUST be low for at least 100 msec after 5V and 3.3V rails are valid.
output is open-drain PWRGD_OUT
3.3V, 3.3V VTR and 5V voltage trip monitors are ALWAYS a source for the PWRGD_OUT.
An internal version of nTHERMTRIP signal from the HW monitor block, can be a source of
PWRGD_OUT, selectable via a bit in the RESGEN register.
A 1.6 sec watchdog timer can be a source for PWRGD_OUT, selectable via a bit in the RESGEN
register. See
The output pulse width is selectable via a strap option (see ), between 200 msec (default) or 500
msec. This pulse is applied to PWRGD_OUT. The RESGEN strap is sampled at
edge of PCIRST# or VCC POR. The following table summarizes the strap option
programmming.
Table
DELAY
200 msec delay (approximate) default
500 msec delay (approximate)
1Dh
(R/W)
18.2.
Section 18.1, "Watchdog Timer for Reset Generation," on page 164
Table 18.2 RESGEN Programming
Table 18.1 RESGEN Strap Option
Reset Generator
Bit[0] WDT2_EN: Enable Watchdog timer Generation / Select
0= WDT Enabled - Source for PWRGD_OUT (Default)
1= WDT Disabled - Not source for PWRGD_OUT
Bit[1] ThermTrip Source Select
0 = Thermtrip not source for PWRGD_OUT ((Default)
1 = Thermtrip source for PWRGD_OUT
Bit[2] WDT2_CTL: WDT input bit
Bit[7:3] Reserved
DATASHEET
163
the deaserting
Rev 0.2 (09-28-04)
for more details.