SCH3112I-NE SMSC [SMSC Corporation], SCH3112I-NE Datasheet - Page 151

• Manufacturer Part Number: SCH3112I-NE
• Description: LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
• Manufacturer: SMSC [SMSC Corporation]

LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
Datasheet
SMSC SCH311X
If Port 92 is enabled, i.e., bit 2 of KRST_GA20 is set to 1, then a pulse is generated by writing a 1 to
bit 0 of the Port 92 Register and this pulse is AND’ed with the pulse generated from the 8042. This
pulse is output on pin KRESET and its polarity is controlled by the GPI/O polarity configuration.
Bit 1 of Port 92, the ALT_A20 signal, is used to force nA20M to the CPU low for support of real mode
compatible software. This signal is externally OR’ed with the A20GATE signal from the keyboard
controller and CPURST to control the nA20M input of the CPU. Writing a 0 to bit 1 of the Port 92
Register forces ALT_A20 low. ALT_A20 low drives nA20M to the CPU low, if A20GATE from the
keyboard controller is also low. Writing a 1 to bit 1 of the Port 92 Register forces ALT_A20 high.
ALT_A20 high drives nA20M to the CPU high, regardless of the state of A20GATE from the keyboard
controller. Upon reset, this signal is driven low.
Latches On Keyboard and Mouse IRQs
The implementation of the latches on the keyboard and mouse interrupts is shown below.
Note: When Port 92 is
writes are ignored and
return undefined
P92
8042
8042
Bit 0
Figure 12.2 Keyboard Latch
P20
KINT
KLATCH Bit
Pulse
Gen
DATASHEET
RD 60
~ ~
14us
KRST_GA2
Bit 2
135
VCC
D
CLR
6us
14us
~ ~
Q
KRST
nALT_RST
6us
KINT
new
KBDRST
Rev 0.2 (09-28-04)