SCH3112I-NE SMSC [SMSC Corporation], SCH3112I-NE Datasheet - Page 148

• Manufacturer Part Number: SCH3112I-NE
• Description: LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
• Manufacturer: SMSC [SMSC Corporation]

Rev 0.2 (09-28-04)
12.4
12.5
12.6
D7
UD
Soft Power-Down Mode
This mode is entered by executing a HALT instruction. The execution of program code is halted until
either RESET is driven active or a data byte is written to the DBBIN register by a master CPU. If this
mode is exited using the interrupt, and the IBF interrupt is enabled, then program execution resumes
with a CALL to the interrupt routine, otherwise the next instruction is executed. If it is exited using
RESET then a normal reset sequence is initiated and program execution starts from program memory
location 0.
Hard Power-Down Mode
This mode is entered by executing a STOP instruction. The oscillator is stopped by disabling the
oscillator
register by a master CPU, this mode will be exited (as above). However, as the oscillator cell will
require an initialization time, either RESET must be held active for sufficient time to allow the oscillator
to stabilize. Program execution will resume as above.
The SCH311X provides the two 8042 interrupts: IBF and the Timer/Counter Overflow.
The SCH311X provides 2K of on-chip ROM and 256 bytes of on-chip RAM.
Host I/F Data Register
The Input Data register and Output Data register are each 8 bits wide. A write to this 8 bit register will
load the Keyboard Data Read Buffer, set the OBF flag and set the KIRQ output if enabled. A read of
this register will read the data from the Keyboard Data or Command Write Buffer and clear the IBF
flag. Refer to the KIRQ and Status register descriptions for more information.
Host I/F Status Register
The Status register is 8 bits wide.
Table 12.3
Status Register
This register is cleared on a reset. This register is read-only for the Host and read/write by the
SCH311X CPU.
UD
C/D
IBF
Interrupts
Memory Configurations
Register Definitions
D6
UD
(0 = data, 1 = command). During a host data/command write operation, this bit is set to “1” if
SA2 = 1 or reset to “0” if SA2 = 0.
data register. Setting this flag activates the SCH311X CPU’s nIBF (MIRQ) interrupt if enabled.
Writable by SCH311X CPU. These bits are user-definable.
(Command Data)-This bit specifies whether the input data register contains data or a command
(Input Buffer Full)- This flag is set to 1 whenever the host system writes data into the input
shows the contents of the Status register.
driver cell.
D5
UD
When either RESET is driven active or a data byte is written to the DBBIN
Table 12.3 Status Register
D4
UD
DATASHEET
LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
132
D3
C/D
D2
UD
D1
IBF
SMSC SCH311X
D0
OBF
Datasheet