SCH3112I-NE SMSC [SMSC Corporation], SCH3112I-NE Datasheet - Page 192

• Manufacturer Part Number: SCH3112I-NE
• Description: LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
• Manufacturer: SMSC [SMSC Corporation]

Rev 0.2 (09-28-04)
20.5.1.1
BIT
10
11
The process to find a match for the scan code stored in the Keyboard Scan Code register meets the
timing constraints as defined by the IBM Personal System/2™ Model 50 and 60 Technical Reference,
dated April 1987. The timing for the keyboard clock and data signals are shown in
Diagrams," on page
Method for Receiving data is as follows:
The wake on specific key logic snoops the keyboard interface for a particular incoming scan code,
which is used to wake the system through a PME event. These scan codes may be comprised of a
single byte or multiple bytes. To determine when the first key code is being received, the wake on
specific key logic begins sampling the data at the first falling edge of the keyboard clock for the start
bit. The data is sampled on each falling edge of the clock. The hardware decodes the byte received
and determines if it is valid (i.e., no parity error). Valid scan code bytes received are compared to the
programmed scan code as determined by bits [3:2] SPEKEY Scan Code located in the PME_STS1
Runtime register located at offset 0x64. If the scan code(s) received matches the value(s) programmed
in the Keyboard Scan Code registers then a wake on specific key status event has occurred. The
wake on specific key status event is mapped to the PME and Power Button logic.
The snooping logic always checks the incoming data byte for a parity error. The hardware samples
the parity bit and checks that the 8 data bits plus the parity bit always have an odd number of 1’s (odd
parity). If a parity error is detected the state machine used to decode the incoming scan code is reset
and begins looking for the first byte in the keyboard scan code sequence.
This process is repeated until a match is found. See
Make Bytes Received from the Keyboard," on page 177 andSection 20.5.3, "System for Decoding
Scan Code Break Bytes Received from the Keyboard," on page
If the scan code received matches the programmed make code stored in the Keyboard Scan Code
registers and no parity error is detected, then it is considered a match. When a match is found and
if the stop bit is 1, a PME wake event (KB_PB_STS-See
of the falling edge of clock 10 of the last byte of the sequence.This wake event may be used to
generate the assertion of the nIO_PME signal when in SX power state or below. PME_STS1 for
description of the PME support for this PME event.
The state machine will reset and repeat the process until it is shut off by setting the SPEKEY_EN bit
in the PME_STS1 register to ‘1’.
1
2
3
4
5
6
7
8
9
Start bit (always 0)
Data bit 0 (least significant bit)
Data bit 1
Data bit 2
Data bit 3
Data bit 4
Data bit 5
Data bit 6
Data bit 7 (most significant bit)
Parity bit (odd parity)
Stop Bit (always 1)
347. (See
Section 29.9, "Keyboard/Mouse Interface Timing," on page
DATASHEET
LPC IO with 8042 KBC, Reset Generation, HWM and Multiple Serial Ports
176
Section 20.5.2, "System for Decoding Scan Code
FUNCTION
Figure
20.1) will be generated within 100usec
178.
Chapter 29, "Timing
SMSC SCH311X
364).
Datasheet