MT41J64M16JT-15E AIT:G Micron, MT41J64M16JT-15E AIT:G Datasheet - Page 10

• Manufacturer Part Number: MT41J64M16JT-15E AIT:G
• Description: DRAM Chip DDR3 SDRAM 1G-Bit 64Mx16 1.5V 96-Pin FBGA
• Manufacturer: Micron

Table 51: Electrical Characteristics and AC Operating Conditions .................................................................... 68
Table 52: Electrical Characteristics and AC Operating Conditions for Speed Extensions .................................... 77
Table 53: Command and Address Setup and Hold Values Referenced at 1 V/ns – AC/DC-Based ........................ 87
Table 54: Derating Values for
Table 55: Derating Values for
Table 56: Derating Values for
Table 57: Derating Values for
Table 58: Minimum Required Time
Table 59: Data Setup and Hold Values at 1 V/ns (DQS, DQS# at 2 V/ns) – AC/DC-Based .................................... 95
Table 60: Derating Values for
Table 61: Derating Values for
Table 62: Derating Values for
Table 63: Required Time
Table 64: Truth Table – Command ................................................................................................................. 102
Table 65: Truth Table – CKE .......................................................................................................................... 104
Table 66: READ Command Summary ............................................................................................................ 106
Table 67: WRITE Command Summary .......................................................................................................... 106
Table 68: READ Electrical Characteristics, DLL Disable Mode ......................................................................... 112
Table 69: Write Leveling Matrix ..................................................................................................................... 116
Table 70: Burst Order .................................................................................................................................... 125
Table 71: MPR Functional Description of MR3 Bits ........................................................................................ 134
Table 72: MPR Readouts and Burst Order Bit Mapping ................................................................................... 135
Table 73: Self Refresh Temperature and Auto Self Refresh Description ............................................................ 168
Table 74: Self Refresh Mode Summary ........................................................................................................... 168
Table 75: Command to Power-Down Entry Parameters .................................................................................. 169
Table 76: Power-Down Modes ....................................................................................................................... 170
Table 77: Truth Table – ODT (Nominal) ......................................................................................................... 180
Table 78: ODT Parameters ............................................................................................................................ 180
Table 79: Write Leveling with Dynamic ODT Special Case .............................................................................. 181
Table 80: Dynamic ODT Specific Parameters ................................................................................................. 182
Table 81: Mode Registers for R
Table 82: Mode Registers for R
Table 83: Timing Diagrams for Dynamic ODT ................................................................................................ 183
Table 84: Synchronous ODT Parameters ........................................................................................................ 188
Table 85: Asynchronous ODT Timing Parameters for All Speed Bins ............................................................... 193
Table 86: ODT Parameters for Power-Down (DLL Off) Entry and Exit Transition Period ................................... 195
PDF: 09005aef84491df3
1Gb_AIT_AAT_DDR3_SDRAM.pdf – Rev. C 8/11 EN
t
VAC Above V
t
t
t
t
t
t
t
IS/
IS/
IS/
IS/
DS/
DS/
DS/
TT,nom
TT(WR)
t
t
t
t
IH – AC175/DC100-Based ............................................................................ 88
IH – AC150/DC100-Based ............................................................................ 88
IH – AC135/DC100-Based ............................................................................ 89
IH – AC125/DC100-Based ............................................................................ 89
t
t
t
DH – AC175/DC100-Based ......................................................................... 96
DH – AC150/DC100-Based ......................................................................... 96
DH – AC135/DC100-Based ......................................................................... 97
t
VAC Above V
............................................................................................................. 182
............................................................................................................. 183
IH(AC)
(Below V
IH(AC)
IL(AC)
for Valid Transition ...................................................... 90
10
) for Valid Transition ................................................ 97
1Gb: x8, x16 Automotive DDR3 SDRAM
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