MT41J64M16JT-15E AIT:G Micron, MT41J64M16JT-15E AIT:G Datasheet - Page 158

• Manufacturer Part Number: MT41J64M16JT-15E AIT:G
• Description: DRAM Chip DDR3 SDRAM 1G-Bit 64Mx16 1.5V 96-Pin FBGA
• Manufacturer: Micron

Figure 80: WRITE Burst
PDF: 09005aef84491df3
1Gb_AIT_AAT_DDR3_SDRAM.pdf – Rev. C 8/11 EN
Command
DQS, DQS#
DQS, DQS#
DQS, DQS#
Address
DQ
DQ
DQ
CK#
CK
1
2
3
3
3
t
t
t
DQSS (NOM)
DQSS (MAX)
DQSS (MIN)
WRITE
Bank,
Col n
T0
NOP
T1
Notes:
WL = AL + CWL
1. NOP commands are shown for ease of illustration; other commands may be valid at
2. The BL8 setting is activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during
3. DI n = data-in for column n.
4. BL8, WL = 5 (AL = 0, CWL = 5).
5.
6.
NOP
T2
these times.
the WRITE command at T0.
t
t
tually ends when DQS no longer drives LOW and DQS# no longer drives HIGH.
DQSS must be met at each rising clock edge.
WPST is usually depicted as ending at the crossing of DQS, DQS#; however,
NOP
T3
t
DQSH
NOP
T4
t
DQSH
t
WPRE
t
t
t
WPRE
DQSH
DQSL
158
t
t
WPRE
DQSL
t
t
DI
DSS
DQSS
n
t
t
DSS
DQSH
t
DQSL
NOP
DI
T5
n
t
t
DSH
DQSS
t
1Gb: x8, x16 Automotive DDR3 SDRAM
t
DQSH
n + 1
DSH
DI
DI
n
t
t
DQSH
DQSL
n + 1
DI
t
t
Micron Technology, Inc. reserves the right to change products or specifications without notice.
n + 2
n + 1
DQSL
DSS
DI
DI
t
DSS
t
DQSH
t
NOP
DQSL
n + 2
T6
DI
t
DSH
t
t
DQSH
n + 3
DSH
n + 2
DI
DI
t
t
DQSH
DQSL
n + 3
DI
t
n + 4
t
DQSL
n + 3
DSS
DI
DI
t
DSS
t
DQSH
t
n + 4
DQSL
NOP
T7
DI
t
DSH
t
t
DQSH
n + 4
n + 5
DSH
DI
DI
t
t
DQSH
DQSL
n + 5
DI
t
n + 6
t
n + 5
DQSL
DSS
DI
DI
t
t
DSS
DQSH
t
DQSL
NOP
n + 6
T8
DI
‹ 2010 Micron Technology, Inc. All rights reserved.
t
DSH
t
t
DQSH
n + 7
n + 6
DSH
DI
DI
WRITE Operation
t
t
t
WPST
DQSH
DQSL
n + 7
Transitioning Data
DI
t
t
WPST
DQSL
t
n + 7
DSS
DI
t
t
DSS
WPST
t
DQSL
NOP
T9
t
WPST ac-
Don’t Care
T10
NOP