MT41J64M16JT-15E AIT:G Micron, MT41J64M16JT-15E AIT:G Datasheet - Page 187

• Manufacturer Part Number: MT41J64M16JT-15E AIT:G
• Description: DRAM Chip DDR3 SDRAM 1G-Bit 64Mx16 1.5V 96-Pin FBGA
• Manufacturer: Micron

Synchronous ODT Mode
ODT Latency and Posted ODT
Timing Parameters
PDF: 09005aef84491df3
1Gb_AIT_AAT_DDR3_SDRAM.pdf – Rev. C 8/11 EN
Synchronous ODT mode is selected whenever the DLL is turned on and locked and
when either R
modes are:
• Any bank active with CKE HIGH
• Refresh mode with CKE HIGH
• Idle mode with CKE HIGH
• Active power-down mode (regardless of MR0[12])
• Precharge power-down mode if DLL is enabled by MR0[12] during precharge power-
In synchronous ODT mode, R
HIGH by a rising clock edge and turns off ODTLoff clock cycles after ODT is registered
LOW by a rising clock edge. The actual on/off times varies by
each clock edge (see Table 84 (page 188)). The ODT latency is tied to the WRITE latency
(WL) by ODTLon = WL - 2 and ODTLoff = WL - 2.
Since write latency is made up of CAS WRITE latency (CWL) and additive latency (AL),
the AL programmed into the mode register (MR1[4, 3]) also applies to the ODT signal.
The device’s internal ODT signal is delayed a number of clock cycles defined by the AL
relative to the external ODT signal. Thus, ODTLon = CWL + AL - 2 and ODTLoff = CWL +
AL - 2.
Synchronous ODT mode uses the following timing parameters: ODTLon, ODTLoff,
ODTH4, ODTH8,
point at which the device leaves High-Z and ODT resistance begins to turn on. Maxi-
mum R
Both are measured relative to ODTLon. The minimum R
the point at which the device starts to turn off ODT resistance. The maximum R
off time (
from ODTLoff.
When ODT is asserted, it must remain HIGH until ODTH4 is satisfied. If a WRITE com-
mand is registered by the DRAM with ODT HIGH, then ODT must remain HIGH until
ODTH4 (BC4) or ODTH8 (BL8) after the WRITE command (see Figure 111 (page 189)).
ODTH4 and ODTH8 are measured from ODT registered HIGH to ODT registered LOW
or from the registration of a WRITE command until ODT is registered LOW.
down
TT
t
AOF [MAX]) is the point at which ODT has reached High-Z. Both are measured
turn-on time (
TT,nom
t
AON, and
or R
t
TT(WR)
AON [MAX]) is the point at which ODT resistance is fully on.
t
187
AOF. The minimum R
TT
is enabled. Based on the power-down definition, these
turns on ODTLon clock cycles after ODT is sampled
1Gb: x8, x16 Automotive DDR3 SDRAM
Micron Technology, Inc. reserves the right to change products or specifications without notice.
TT
turn-on time (
Synchronous ODT Mode
TT
turn-off time (
t
AON and
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t
AON [MIN]) is the
t
AOF around
t
AOF [MIN]) is
TT
turn