MT41J64M16JT-15E AIT:G Micron, MT41J64M16JT-15E AIT:G Datasheet - Page 169

• Manufacturer Part Number: MT41J64M16JT-15E AIT:G
• Description: DRAM Chip DDR3 SDRAM 1G-Bit 64Mx16 1.5V 96-Pin FBGA
• Manufacturer: Micron

Power-Down Mode
Table 75: Command to Power-Down Entry Parameters
PDF: 09005aef84491df3
1Gb_AIT_AAT_DDR3_SDRAM.pdf – Rev. C 8/11 EN
DRAM Status
Idle or active
Idle or active
Power-down
Active
Active
Active
Active
Active
Idle
Idle
WRITEAP: BL8OTF, BL8MRS,
Last Command Prior to
WRITE: BL8OTF, BL8MRS,
MODE REGISTER SET
WRITEAP: BC4MRS
Note:
READ or READAP
WRITE: BC4MRS
PRECHARGE
CKE LOW
ACTIVATE
REFRESH
REFRESH
BC4OTF
BC4OTF
Power-down is synchronously entered when CKE is registered LOW coincident with a
NOP or DES command. CKE is not allowed to go LOW while an MRS, MPR, ZQCAL,
READ, or WRITE operation is in progress. CKE is allowed to go LOW while any of the
other legal operations (such as ROW ACTIVATION, PRECHARGE, auto precharge, or RE-
FRESH) are in progress. However, the power-down I
until such operations have completed. Depending on the previous DRAM state and the
command issued prior to CKE going LOW, certain timing constraints must be satisfied
(as noted in Table 75). Timing diagrams detailing the different power-down mode entry
and exits are shown in Figure 92 (page 171) through Figure 101 (page 176).
Entering power-down disables the input and output buffers, excluding CK, CK#, ODT,
CKE, and RESET#. NOP or DES commands are required until
fied, at which time all specified input/output buffers are disabled. The DLL should be in
a locked state when power-down is entered for the fastest power-down exit timing. If
the DLL is not locked during power-down entry, the DLL must be reset after exiting
power-down mode for proper READ operation as well as synchronous ODT operation.
During power-down entry, if any bank remains open after all in-progress commands are
complete, the DRAM will be in active power-down mode. If all banks are closed after all
in-progress commands are complete, the DRAM will be in precharge power-down
mode. Precharge power-down mode must be programmed to exit with either a slow exit
mode or a fast exit mode. When entering precharge power-down mode, the DLL is
turned off in slow exit mode or kept on in fast exit mode.
The DLL also remains on when entering active power-down. ODT has special timing
constraints when slow exit mode precharge power-down is enabled and entered. Refer
to Asynchronous ODT Mode (page 192) for detailed ODT usage requirements in slow
1. If slow-exit mode precharge power-down is enabled and entered, ODT becomes asyn-
chronous
t
XPDLL after CKE goes HIGH.
1
t
ANPD prior to CKE going LOW and remains asynchronous until
Parameter (Min)
t
t
t
WRAPDEN
t
t
MRSPDEN
ACTPDEN
t
t
WRPDEN
REFPDEN
RDPDEN
PRPDEN
t
XPDLL
169
1Gb: x8, x16 Automotive DDR3 SDRAM
Greater of 10
WL + 4
WL + 2
WL + 4
WL + 2
Micron Technology, Inc. reserves the right to change products or specifications without notice.
Parameter Value
RL + 4
t
t
CK + WR + 1
CK + WR + 1
t
t
t
CK +
CK +
1
1
1
MOD
t
CK + 1
t
t
t
CK
CK
CK
t
CK or 24ns
t
t
DD
WR/
WR/
t
CK
specifications are not applicable
t
t
CK
CK
t
t
CK
CK
t
Power-Down Mode
CPDED has been satis-
‹ 2010 Micron Technology, Inc. All rights reserved.
Figure 100 (page 175)
Figure 102 (page 176)
Figure 101 (page 176)
Figure 99 (page 175)
Figure 95 (page 173)
Figure 96 (page 173)
Figure 96 (page 173)
Figure 97 (page 174)
Figure 97 (page 174)
Figure 98 (page 174)
Figure
t
ANPD +