MT41J64M16JT-15E AIT:G Micron, MT41J64M16JT-15E AIT:G Datasheet - Page 116

• Manufacturer Part Number: MT41J64M16JT-15E AIT:G
• Description: DRAM Chip DDR3 SDRAM 1G-Bit 64Mx16 1.5V 96-Pin FBGA
• Manufacturer: Micron

Table 69: Write Leveling Matrix
Note 1 applies to the entire table
PDF: 09005aef84491df3
1Gb_AIT_AAT_DDR3_SDRAM.pdf – Rev. C 8/11 EN
Leveling
Disabled
Enabled
MR1[7]
Write
(1)
MR1[12] MR1[2, 6, 9]
Disabled
Enabled
Output
Buffers
(1)
(0)
Notes:
See normal operations
R
Value
When write leveling is enabled, the rising edge of DQS samples CK, and the prime DQ
outputs the sampled CK’s status. The prime DQ for a x4 or x8 configuration is DQ0 with
all other DQ (DQ[7:1]) driving LOW. The prime DQ for a x16 configuration is DQ0 for the
lower byte and DQ8 for the upper byte. It outputs the status of CK sampled by LDQS
and UDQS. All other DQ (DQ[7:1], DQ[15:9]) continue to drive LOW. Two prime DQ on a
x16 enable each byte lane to be leveled independently.
The write leveling mode register interacts with other mode registers to correctly config-
ure the write leveling functionality. Besides using MR1[7] to disable/enable write level-
ing, MR1[12] must be used to enable/disable the output buffers. The ODT value, burst
length, and so forth need to be selected as well. This interaction is shown in Table 69. It
should also be noted that when the outputs are enabled during write leveling mode, the
DQS buffers are set as inputs, and the DQ are set as outputs. Additionally, during write
leveling mode, only the DQS strobe terminations are activated and deactivated via the
ODT ball. The DQ remain disabled and are not affected by the ODT ball.
120
120
TT,nom
n/a
n/a
1. Expected usage if used during write leveling: Case 1 may be used when DRAM are on a
2. Since the DRAM DQS is not being driven (MR1[12] = 1), DQS ignores the input strobe,
3. Since the DRAM DQS is being driven (MR1[12] = 0), DQS captures the input strobe, and
, or
, or
dual-rank module and on the rank not being leveled or on any rank of a module not
being leveled on a multislot system. Case 2 may be used when DRAM are on any rank of
a module not being leveled on a multislot system. Case 3 is generally not used. Case 4 is
generally used when DRAM are on the rank that is being leveled.
and all R
only some R
ODT Ball
DRAM
High
High
Low
Low
TT,nom
TT,nom
values are allowed. This simulates a normal standby state to DQS.
DQS
Off
Off
On
On
values are allowed. This simulates a normal write state to DQS.
R
DRAM
TT,nom
DQ
Off
116
Write leveling not enabled
DQS not receiving: not terminated
Prime DQ High-Z: not terminated
Other DQ High-Z: not terminated
DQS not receiving: terminated by R
Prime DQ High-Z: not terminated
Other DQ High-Z: not terminated
DQS receiving: not terminated
Prime DQ driving CK state: not terminated
Other DQ driving LOW: not terminated
DQS receiving: terminated by R
Prime DQ driving CK state: not terminated
Other DQ driving LOW: not terminated
1Gb: x8, x16 Automotive DDR3 SDRAM
Micron Technology, Inc. reserves the right to change products or specifications without notice.
DRAM State
‹ 2010 Micron Technology, Inc. All rights reserved.
TT
TT
Write Leveling
Case Notes
0
1
2
3
4
2
3