MT41J64M16JT-15E AIT:G Micron, MT41J64M16JT-15E AIT:G Datasheet - Page 109

• Manufacturer Part Number: MT41J64M16JT-15E AIT:G
• Description: DRAM Chip DDR3 SDRAM 1G-Bit 64Mx16 1.5V 96-Pin FBGA
• Manufacturer: Micron

DLL Disable Mode
PDF: 09005aef84491df3
1Gb_AIT_AAT_DDR3_SDRAM.pdf – Rev. C 8/11 EN
• All other self refresh mode exit timing requirements are met
If the DLL is disabled by the mode register (MR1[0] can be switched during initialization
or later), the DRAM is targeted, but not guaranteed, to operate similarly to the normal
mode, with a few notable exceptions:
• The DRAM supports only one value of CAS latency (CL = 6) and one value of CAS
• DLL disable mode affects the read data clock-to-data strobe relationship (
• In normal operation (DLL on),
The ODT feature (including dynamic ODT) is not supported during DLL disable mode.
The ODT resistors must be disabled by continuously registering the ODT ball LOW by
programming R
mode.
Specific steps must be followed to switch between the DLL enable and DLL disable
modes due to a gap in the allowed clock rates between the two modes (
and
clock rate gap is during self refresh mode. Thus, the required procedure for switching
from the DLL enable mode to the DLL disable mode is to change frequency during self
refresh:
WRITE latency (CWL = 6).
but not the read data-to-data strobe relationship (
required to line up the read data with the controller time domain when the DLL is dis-
abled.
cycles after the READ command. In DLL disable mode,
cles after the READ command. Additionally, with the DLL disabled, the value of
t
1. Starting from the idle state (all banks are precharged, all timings are fulfilled, ODT
2. Enter self refresh mode after
3. After
4. Self refresh may be exited when the clock is stable with the new frequency for
5. The DRAM will be ready for its next command in the DLL disable mode after the
DQSCK could be larger than
t
CK [DLL_DIS] MIN, respectively). The only time the clock is allowed to cross this
is turned off, and R
DLL.
t
greater of
with appropriate timings met.
CKSRX. After
t
CKSRE is satisfied, change the frequency to the desired clock rate.
t
TT,nom
MRD or
t
XS is satisfied, update the mode registers with appropriate values.
MR1[9, 6, 2] and R
TT,nom
t
MOD has been satisfied. A ZQCL command should be issued
109
and R
t
CK.
t
DQSCK starts from the rising clock edge AL + CL
t
1Gb: x8, x16 Automotive DDR3 SDRAM
MOD has been satisfied.
TT(WR)
Micron Technology, Inc. reserves the right to change products or specifications without notice.
TT(WR)
are High-Z), set MR1[0] to 1 to disable the
MR2[10, 9] to 0 while in the DLL disable
t
DQSQ,
t
DQSCK starts AL + CL - 1 cy-
t
QH). Special attention is
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t
CK [AVG] MAX
Commands
t
DQSCK),