MT41J64M16JT-15E AIT:G Micron, MT41J64M16JT-15E AIT:G Datasheet - Page 110

• Manufacturer Part Number: MT41J64M16JT-15E AIT:G
• Description: DRAM Chip DDR3 SDRAM 1G-Bit 64Mx16 1.5V 96-Pin FBGA
• Manufacturer: Micron

Figure 38: DLL Enable Mode to DLL Disable Mode
PDF: 09005aef84491df3
1Gb_AIT_AAT_DDR3_SDRAM.pdf – Rev. C 8/11 EN
Command
ODT
CKE
CK#
CK
9
6
MRS
T0
2
Notes:
t
MOD
NOP
T1
A similar procedure is required for switching from the DLL disable mode back to the
DLL enable mode. This also requires changing the frequency during self refresh mode
(see Figure 39 (page 111)).
1. Any valid command.
2. Disable DLL by setting MR1[0] to 1.
3. Enter SELF REFRESH.
4. Exit SELF REFRESH.
5. Update the mode registers with the DLL disable parameters setting.
6. Starting with the idle state, R
7. Change frequency.
8. Clock must be stable
9. Static LOW in the case that R
1. Starting from the idle state (all banks are precharged, all timings are fulfilled, ODT
2. After
3. Self refresh may be exited when the clock is stable with the new frequency for
4. After another
5. The DRAM will be ready for its next command in the DLL enable mode after the
is turned off, and R
t
ues. At a minimum, set MR1[0] to 0 to enable the DLL. Wait
to 1 to enable DLL RESET.
the appropriate values.
greater of
mand or function requiring a locked DLL, a delay of
be satisfied. A ZQCL command should be issued with the appropriate timings met.
Ta0
SRE
CKSRX. After
3
t
CKSRE is satisfied, change the frequency to the new clock rate.
t
CKSRE
NOP
Ta1
t
MRD or
t
t
MRD delay is satisfied, update the remaining mode registers with
XS is satisfied, update the mode registers with the appropriate val-
t
CKESR
Tb0
TT,nom
t
t
MOD has been satisfied. However, before applying any com-
CKSRX.
7
110
and R
TT,nom
TT
Tc0
1Gb: x8, x16 Automotive DDR3 SDRAM
is in the High-Z state.
t
CKSRX
TT(WR)
or R
Micron Technology, Inc. reserves the right to change products or specifications without notice.
8
Td0
SRX
TT(WR)
are High-Z), enter self refresh mode.
4
is enabled; otherwise, static LOW or HIGH.
NOP
Td1
t
XS
t
Indicates break
in time scale
DLLK after DLL RESET must
MRS
Te0
‹ 2010 Micron Technology, Inc. All rights reserved.
5
t
MRD, then set MR0[8]
t
NOP
MOD
Te1
Commands
Don’t Care
Valid
Valid
Valid 1
Tf0
1
1