MT41J64M16JT-15E AIT:G Micron, MT41J64M16JT-15E AIT:G Datasheet - Page 120

• Manufacturer Part Number: MT41J64M16JT-15E AIT:G
• Description: DRAM Chip DDR3 SDRAM 1G-Bit 64Mx16 1.5V 96-Pin FBGA
• Manufacturer: Micron

Initialization
PDF: 09005aef84491df3
1Gb_AIT_AAT_DDR3_SDRAM.pdf – Rev. C 8/11 EN
The following sequence is required for power-up and initialization, as shown in Fig-
ure 45 (page 121):
10. Issue a ZQCL command to calibrate R
11. When
1. Apply power. RESET# is recommended to be below 0.2 × V
2. Until stable power, maintain RESET# LOW to ensure the outputs remain disabled
3. CKE must be LOW 10ns prior to RESET# transitioning HIGH.
4. After RESET# transitions HIGH, wait 500μs (minus one clock) with CKE LOW.
5. After the CKE LOW time, CKE may be brought HIGH (synchronously) and only
6. After CKE is registered HIGH and after
7. Issue an MRS command to MR3 with the applicable settings.
8. Issue an MRS command to MR1 with the applicable settings, including enabling
9. Issue an MRS command to MR0 with the applicable settings, including a DLL RE-
to ensure the outputs remain disabled (High-Z) and ODT off (R
All other inputs, including ODT, may be undefined.
During power-up, either of the following conditions may exist and must be met:
• Condition A:
• Condition B:
(High-Z). After the power is stable, RESET# must be LOW for at least 200μs to be-
gin the initialization process. ODT will remain in the High-Z state while RESET# is
LOW and until CKE is registered HIGH.
NOP or DES commands may be issued. The clock must be present and valid for at
least 10ns (and a minimum of five clocks) and ODT must be driven LOW at least
t
continuously registered HIGH until the full initialization process is complete.
may be issued. Issue an MRS (LOAD MODE) command to MR2 with the applicable
settings (provide LOW to BA2 and BA0 and HIGH to BA1).
the DLL and configuring ODT.
SET command.
temperature (PVT). Prior to normal operation,
normal operation.
IS prior to CKE being registered HIGH. When CKE is registered HIGH, it must be
– V
– Both V
– V
– V
– V
– V
– No slope reversals are allowed in the power supply ramp for this condition.
ramped with a maximum delta voltage between them of V 300mV. Slope re-
versal of any power supply signal is allowed. The voltage levels on all balls oth-
er than V
one side, and must be greater than or equal to V
t
directly to the device; however,
avoid device latchup.
V
DD
REFDQ
TT
DD
DDQ
DDPR
t
DLLK and
is limited to 0.95V when the power ramp is complete and is not applied
and V
may be applied before or at the same time as V
may be applied before or at the same time as V
DD
= 200ms.
tracks V
DD
and V
DDQ
, V
t
DLLK (512) cycles of clock input are required to lock the DLL.
t
DDQ
ZQinit have been satisfied, the DDR3 SDRAM will be ready for
are driven from a single-power converter output and are
DD
DDQ
, V
× 0.5, V
120
power supplies ramp to V
SS
, V
SSQ
1Gb: x8, x16 Automotive DDR3 SDRAM
REFCA
must be less than or equal to V
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
tracks V
VTD should be greater than or equal to 0 to
TT
t
XPR has been satisfied, MRS commands
and R
DD
ON
× 0.5.
t
ZQinit must be satisfied.
values for the process voltage
DD,min
SSQ
DDQ
and V
and V
TT
‹ 2010 Micron Technology, Inc. All rights reserved.
DDQ
, V
.
REFDQ
SS
DDQ,min
during power ramp
TT
DDQ
on the other side.
Initialization
is also High-Z).
, and V
and V
within
DD
REFCA
on
.