MT41J64M16JT-15E AIT:G Micron, MT41J64M16JT-15E AIT:G Datasheet - Page 164

• Manufacturer Part Number: MT41J64M16JT-15E AIT:G
• Description: DRAM Chip DDR3 SDRAM 1G-Bit 64Mx16 1.5V 96-Pin FBGA
• Manufacturer: Micron

Figure 89: WRITE (BC4 OTF) to PRECHARGE
DQ Input Timing
PDF: 09005aef84491df3
1Gb_AIT_AAT_DDR3_SDRAM.pdf – Rev. C 8/11 EN
Command 1
DQS, DQS#
Address 3
DQ 4
CK#
CK
WRITE
Bank,
Col n
T0
NOP
T1
Notes:
Figure 80 (page 158) shows the strobe-to-clock timing during a WRITE burst. DQS,
DQS# must transition within 0.25
data and data mask setup and hold timings are measured relative to the DQS, DQS#
crossing, not the clock crossing.
The WRITE preamble and postamble are also shown in Figure 80 (page 158). One clock
prior to data input to the DRAM, DQS must be HIGH and DQS# must be LOW. Then for
a half clock, DQS is driven LOW (DQS# is driven HIGH) during the WRITE preamble,
t
to the DRAM during the WRITE postamble,
Data setup and hold times are also shown in Figure 80 (page 158). All setup and hold
times are measured from the crossing points of DQS and DQS#. These setup and hold
values pertain to data input and data mask input.
Additionally, the half period of the data input strobe is specified by
WPRE. Likewise, DQS must be kept LOW by the controller after the last data is written
1. NOP commands are shown for ease of illustration; other commands may be valid at
2. The write recovery time (
3. The BC4 setting is activated by MR0[1:0] = 01 and A12 = 0 during the WRITE command
4. DI n = data-in for column n.
5. BC4 (OTF), WL = 5, RL = 5.
NOP
T2
these times.
fies the last burst WRITE cycle until the PRECHARGE command can be issued to the same
bank.
at T0.
WL = 5
NOP
T3
NOP
T4
t
WPRE
t
164
WR) is referenced from the rising clock edge at T9.
NOP
T5
t
DI
n
CK of the clock transitions, as limited by
1Gb: x8, x16 Automotive DDR3 SDRAM
n + 1
DI
Micron Technology, Inc. reserves the right to change products or specifications without notice.
n + 2
NOP
T6
DI
t
WPST.
n + 3
DI
t
WPST
NOP
T7
Indicates break
in time scale
‹ 2010 Micron Technology, Inc. All rights reserved.
NOP
T8
WRITE Operation
t
Transitioning Data
DQSH and
NOP
T9
t
DQSS. All
t
t
WR
WR speci-
t
2
DQSL.
Don’t Care
Valid
PRE
Tn