MT41J64M16JT-15E AIT:G Micron, MT41J64M16JT-15E AIT:G Datasheet - Page 134

• Manufacturer Part Number: MT41J64M16JT-15E AIT:G
• Description: DRAM Chip DDR3 SDRAM 1G-Bit 64Mx16 1.5V 96-Pin FBGA
• Manufacturer: Micron

Figure 55: Multipurpose Register (MPR) Block Diagram
Table 71: MPR Functional Description of MR3 Bits
MPR Functional Description
PDF: 09005aef84491df3
1Gb_AIT_AAT_DDR3_SDRAM.pdf – Rev. C 8/11 EN
MR3[2]
MPR
0
1
(see Table 72 (page 135))
MPR READ Function
“Don’t Care”
Notes:
MR3[1:0]
A[1:0]
To enable the MPR, the MRS command is issued to MR3, and MR3[2] = 1. Prior to issu-
ing the MRS command, all banks must be in the idle state (all banks are precharged,
and
are redirected to the multipurpose register. The resulting operation when either a READ
or a RDAP command is issued, is defined by MR3[1:0] when the MPR is enabled (see
Table 72 (page 135)). When the MPR is enabled, only READ or RDAP commands are al-
lowed until a subsequent MRS command is issued with the MPR disabled (MR3[2] = 0).
Power-down mode, self refresh, and any other nonREAD/RDAP commands are not al-
lowed during MPR enable mode. The RESET function is supported during MPR enable
mode.
The MPR JEDEC definition enables either a prime DQ (DQ0 on a x4 and a x8; on a x16,
DQ0 = lower byte and DQ8 = upper byte) to output the MPR data with the remaining
DQs driven LOW, or for all DQs to output the MPR data. The MPR readout supports
Memory core
1. A predefined data pattern can be read out of the MPR with an external READ com-
2. MR3[2] defines whether the data flow comes from the memory core or the MPR. When
t
RP is met). When the MPR is enabled, any subsequent READ or RDAP commands
mand.
the data flow is defined, the MPR contents can be read out continuously with a regular
READ or RDAP command.
DQ, DM, DQS, DQS#
MR3[2] = 1 (MPR on)
Enable MPR mode, subsequent READ/RDAP commands defined by bits 1 and
MR3[2] = 0 (MPR off)
All subsequent READs come from the DRAM memory array
All subsequent WRITEs go to the DRAM memory array
134
predefined data for READs
Normal operation, no MPR transaction
1Gb: x8, x16 Automotive DDR3 SDRAM
Multipurpose register
Micron Technology, Inc. reserves the right to change products or specifications without notice.
Function
2
Mode Register 3 (MR3)
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